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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions - most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 1 mips throughput per mhz ? on-chip 2-cycle multiplier ? data and non-volatile program memory ? 8k bytes flash of in-system programmable program memory ? endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? 512 bytes of in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 512 bytes internal sram ? programming lock for flash program and eeprom data security ? on chip debug interface (debugwire) ? peripheral features ? two 12-bit high speed psc (power stage controllers) with 4-bit resolution enhancement ? non overlapping inverted pwm output pins with flexible dead-time ? variable pwm duty cycle and frequency ? synchronous update of all pwm registers ? auto stop function for event driven pfc implementation ? less than 25 hz step width at 150 khz output frequency ? psc2 with four output pins and output matrix ? one 8-bit general purpose timer/counte r with separate prescaler and capture mode ? one 16-bit general purpose timer/counter with separate prescaler, compare mode and capture mode ? master/slave spi serial interface ? 10-bit adc ? 8 single ended channels and 1 fully differential adc channel pair ? programmable gain (5x, 10x, 20x, 40x on differential channel) ? internal reference voltage ? two analog comparator with resistor-array to adjust comparison voltage ? 4 external interrupts ? programmable watchdog timer with separate on-chip oscillator ? special microcontroller features ? low power idle, noise reduction, and power down modes ? power on reset and programmable brown out detection ? flag array in bit-programmable i/o space (4 bytes) ? in-system programmable via spi port ? internal calibrated rc oscillator ( 8 mhz) ? on-chip pll for fast pwm ( 32 mhz, 64 mhz) and cpu (16 mhz) 4378c?avr?09/08 8-bit microcontroller with 8k bytes in-system programmable flash at90pwm1
2 4378c?avr?09/08 at90pwm1 ? operating voltage: 2.7v - 5.5v ? extended operating temperature: ? -40c to +105 1. history 2. disclaimer typical values contained in this datasheet ar e based on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max val- ues will be available after the device is characterized. 3. pin configurations figure 3-1. soic 24-pin package product revision at90pwm1 first revision of parts 3 4378c?avr?09/08 at90pwm1 figure 3-2. qfn 32 -pin package 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pscin2/oc1a/miso_a) pd2 (oc0a/ss/mosi_a) pd3 nc vcc gnd nc nc (miso/pscout20) pb0 pb4 (amp0+) pb3 (amp0-) nc aref agnd avcc nc nc 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (mosi/pscout21) pb1 (oc0b/xtal1) pe1 (adc0/xtal2) pe2 (adc1/icp1_a/sck_a) pd4 (adc2/acmp2 ) pd5 (adc3/acmpm/int0) pd6 (acmp0) pd7 (adc5/int1) pb2 pd1 (pscin0/clko) pe0 (reset/ocd) nc pd0 (pscout00/ss_a) pb7 (adc4/pscout01/sck) pb6 (adc7/icp1b) pb5 (adc6/int2) nc at90pwm1 qfn 32 4 4378c?avr?09/08 at90pwm1 3.1 pin descriptions : table 3-1. pin out description qfn32 s024 pin number mnemonic type name, function & alternate function 5 7 gnd power ground: 0v reference 20 18 agnd power analog ground: 0v reference for analog part 4 6 vcc power power supply: 19 17 avcc power analog power supply: this is the power supply voltage for analog part for a normal use this pin must be connected. 21 19 aref power analog reference : reference for analog converter . this is the reference voltage of the a/d conv erter. as output, can be used by external analog 88pboi/o miso (spi master in slave out) pscout20 output 99pb1i/o mosi (spi master out slave in) pscout21 output 16 16 pb2 i/o adc5 (analog input channel5 ) int1 23 20 pb3 i/o amp0- (analog differential amplifier 0 input channel ) 24 21 pb4 i/o amp0+ (analog differential amplifier 0 input channel ) 26 22 pb5 i/o adc6 (analog input channel 6) int 2 27 23 pb6 i/o adc7 (analog input channel 7) icp1b (timer 1 input capture alternate input) pscout11 output 28 24 pb7 i/o pscout01 output adc4 (analog input channel 4) sck (spi clock) 29 1 pd0 i/o pscout00 output xck (uart transfer clock) ss_a (alternate spi slave select) 32 3 pd1 i/o pscin0 (psc 0 digital input ) clko (system clock output) 14pd2i/o pscin2 (psc 2 digital input) oc1a (timer 1 output compare a) miso_a (programming & alternate spi master in slave out) 25pd3i/o txd (dali/uart tx data) oc0a (timer 0 output compare a) ss (spi slave select) mosi_a (programming & alternate master out spi slave in) 5 4378c?avr?09/08 at90pwm1 4. overview the at90pwm1 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the at90pwm1 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. 12 12 pd4 i/o adc1 (analog input channel 1) rxd (dali/uart rx data) icp1a (timer 1 input capture) sck_a (programming & alternate spi clock) 13 13 pd5 i/o adc2 (analog input channel 2) acmp2 (analog comparator 2 positive input ) 14 14 pd6 i/o adc3 (analog input channel 3 ) acmpm reference for analog comparators int0 15 15 pd7 i/o acmp0 (analog comparator 0 positive input ) 31 2 pe0 i/o or i reset (reset input) ocd (on chip debug i/o) 10 10 pe1 i/o xtal1: xtal input oc0b (timer 0 output compare b) 11 11 pe2 i/o xtal2: xtal output adc0 (analog input channel 0) table 3-1. pin out description (continued) qfn32 s024 pin number mnemonic type name, function & alternate function 6 4378c?avr?09/08 at90pwm1 4.1 block diagram figure 4-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instructi on executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional cisc microcontrollers. the at90pwm1 provides the following features: 8k bytes of in-system programmable flash with read-while-write capabilities, 512 bytes eeprom, 512 bytes sram, 53 general purpose i/o lines, 32 general purpose working registers, 2 power stage controllers, two flexible timer/counters with compare modes and pwm, an 8-channel 10-bit adc with two differential 7 4378c?avr?09/08 at90pwm1 input stage with programmable gain, a programmable watchdog timer with internal oscillator, an spi serial port, an on-chip debug system and four software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi ports and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip function s until the next interrupt or hardware reset. the adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switch- ing noise during adc conversions. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. the device is manufactured using atmel?s high-density nonvolatile memory technology. the on- chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel at90pwm1 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. the at90pwm1 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4.2 pin descriptions 4.2.1 vcc digital supply voltage. 4.2.2 gnd ground. 4.2.3 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive c haracteristics with both high sink and source capability. as inputs, port b pins that are exte rnally pulled low will sour ce current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the at90pwm1 as listed on page 65 . 4.2.4 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with both high sink and source capability. as inputs, port d pins that are exte rnally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the at90pwm1 as listed on page 68 . 8 4378c?avr?09/08 at90pwm1 4.2.5 port e (pe2..0) reset/ xtal1/ xtal2 port e is an 3-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive c haracteristics with both high sink and source capability. as inputs, port e pins that are exte rnally pulled low will sour ce current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the rstdisbl fuse is programmed, pe0 is used as an i/o pin. note that the electrical char- acteristics of pe0 differ from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pe0 is used as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 9-1 on page 43 . shorter pulses are not guaranteed to generate a reset. depending on the clock selection fuse settings, pe1 can be used as input to the inverting oscil- lator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pe 2 can be used as output from the inverting oscillator amplifier. the various special features of port e are elaborated in ?alternate functions of port e? on page 71 and ?clock systems and their distribution? on page 27 . 4.2.6 avcc avcc is the supply voltage pin for the a/d conver ter on port f. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 4.2.7 aref this is the analog reference pin for the a/d converter. 4.3 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 9 4378c?avr?09/08 at90pwm1 5. avr cpu core 5.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cp u must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 architectural overview figure 5-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 10 4378c?avr?09/08 at90pwm1 the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typ- ical alu operation, two operands are output from t he register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for lo ok up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm (store program memory) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher is the priority. the i/o memory space contains 64 addresses fo r cpu peripheral functions as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the regist er file, 0x20 - 0x5f. in addition, the at90pwm1 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 5.3 alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycl e, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 11 4378c?avr?09/08 at90pwm1 5.4 status register the status register contains information about t he result of the most recently executed arith- metic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set to enabled the interrupts. the individual interrupt enable control is then performed in separate c ontrol registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware a fter an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between t he negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 12 4378c?avr?09/08 at90pwm1 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for detailed information. 5.5 general purpose register file the register file is optimized for the avr enha nced risc instruction set. in order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 5-2 shows the structure of the 32 general purpose working registers in the cpu. figure 5-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 5-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the us er data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 5.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 5-3 . 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 13 4378c?avr?09/08 at90pwm1 figure 5-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x100. the stack pointer is decreme nted by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 5.7 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 1514131211109 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 14 4378c?avr?09/08 at90pwm1 figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 5-4. the parallel instruction fetches and instruction executions figure 5-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 5-5. single cycle alu operation 5.8 reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory program- ming? on page 219 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 53 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is psc2 capt ? the psc2 capture event. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 53 for more infor- mation. the reset vector can also be moved to the start of the boot flash section by clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 15 4378c?avr?09/08 at90pwm1 programming the bootrst fuse, see ?boot loader support ? read-while-write self-pro- gramming? on page 205 . 5.8.1 interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding inter- rupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. when the avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrupts will be immediately disabled. no interrupt will be executed after the cli instru ction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence.. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 17 4378c?avr?09/08 at90pwm1 6. memories this section describes the different memories in the at90pwm1. the avr architecture has two main memory spaces, the data memory and the program memory space. in addition, the at90pwm1 features an eeprom memory for data storage. all three memory spaces are linear and regular. 6.1 in-system reprogrammabl e flash program memory the at90pwm1 contains 8k bytes on-chip in-system reprogrammable flash memory for pro - gram storage. since all avr instructions are 16 or 32 bits wide, the flash is organized as 4k x 16. for software security, the flash program memo ry space is divided into two sections, boot program section and application program section. the flash memory has an endurance of at least 10,000 write/erase cycles. the at90pwm1 program counter (pc) is 12 bits wide, thus addressing the 4k program memory locations. the operation of boot program section and associated boot lock bits for software protection are described in detail in ?boot loader support ? read-while-write self-programming? on page 205 . ?memory programming? on page 219 contains a detailed description on flash programming in spi or parallel programming mode. constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory. timing diagrams for instruction fetch and execution are presented in ?instruction execution tim - ing? on page 13 . figure 1. program memory map 6.2 sram data memory figure 2 shows how the at90pwm1 sram memory is organized. 0x0000 0x0fff program memory application flash section boot flash section 18 4378c?avr?09/08 at90pwm1 the at90pwm1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instruc - tions can be used. the lower 768 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 512 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace - ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre - ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o registers, and the 512 bytes of internal data sram in the at90pwm1 are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 12 . figure 2. data memory map 6.2.1 sram data access times this section describes the general access timing concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 3 . 32 registers 64 i/o registers internal sram (512 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x02ff 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 19 4378c?avr?09/08 at90pwm1 figure 3. on-chip data sram access cycles 6.3 eeprom data memory the at90pwm1 contains 512 bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi and parallel data downloading to the eeprom, see ?serial downloading? on page 234 , and ?parallel programming parameters, pin mapping, and com - mands? on page 223 respectively. 6.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 2 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instructions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as mini mum for the clock frequency used. for details on how to avoid problems in these situations see see ?preventing eeprom corruption? on page 24. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control register for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. 6.3.2 the eeprom address registers ? eearh and eearl clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction bit 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? eear8 eearh 20 4378c?avr?09/08 at90pwm1 ? bits 15..9 ? reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bits 8..0 ? eear8..0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 512 bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 511. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 6.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read operation, the eedr contains the data read out from the eeprom at the address given by eear. 6.3.4 the eeprom control register ? eecr ? bits 7..6 ? reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bits 5..4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines which programming action that will be trig - gered when writing eewe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 1 . while eewe is set, any write to eepmn will be ignored. du ring reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7654 3 2 10 read/write rrrr r r rr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 x xxxx x x xx bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 210 ? ? eepm1 eepm0 eerie eemwe eewe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 table 1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 21 4378c?avr?09/08 at90pwm1 ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant inter - rupt when eewe is cleared. the interrupt will not be generated during eeprom write or spm. ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whet her setting eewe to one causes the eeprom to be written. when eemwe is set, setting eewe within four cl ock cycles will write data to the eeprom at the selected address if eemwe is zero, se tting eewe will have no effect. when eemwe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be written to one before a logical one is written to eewe, oth - erwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program memory control and status register) becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writing a zero to eewe in eecr. 6. within four clock cycles after setting eemwe, write a logical one to eewe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming? on page 205 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared by hardware. the user soft - ware can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes o ne instruction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eewe bit before starti ng the read operation. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. 22 4378c?avr?09/08 at90pwm1 the calibrated oscillator is used to time the eeprom accesses. table 2 lists the typical pro - gramming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoing spm command to finish. table 2. eeprom programming time. symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 26368 3.3 ms 23 4378c?avr?09/08 at90pwm1 table 1. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 26 4378c?avr?09/08 at90pwm1 gpior37 gpior36 gpior35 gpior34 gpio r33 gpior32 gpior31 gpior30 gpior3 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 27 4378c?avr?09/08 at90pwm1 7. system clock 7.1 clock systems and their distribution figure 7-1 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 37 . the clock systems are detailed below. figure 7-1. clock distribution at90pwm2/3 7.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general purpose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 7.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, spi, usart. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. general i/o modules adc cpu core ram clk i/o avr clock control unit clk cpu flash and eeprom clk flash clk adc source clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator (crystal oscillator) external clock psc0/1/2 pll clk pll multiplexer pll input 28 4378c?avr?09/08 at90pwm1 7.1.3 flash clock ? clk flash the flash clock controls operation of the flash interface. the flash clock is usually active simul - taneously with the cpu clock. 7.1.4 pll clock ? clk pll the pll clock allows the psc modules to be clocked directly from a 64/32 mhz clock. a 16 mhz clock is also derived for the cpu. 7.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 7.2 clock sources the device has the following clock source options, selectable by flash fuse bits as illustrated table 7-1. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. the various choices for each clocking option is given in the following sections. when the cpu wakes up from power-down or power-save, the selected clock source is used to time the start- up, ensuring stable oscillator operation before instruction execution starts. when the cpu starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. the watchdog oscillator is used for timing this real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 7-2 . the table 7-1. device clocking options select at90pwm1 device clocking option system clock pll input cksel3..0 (1) 1.for all fuses ?1? means unprogrammed while ?0? means programmed external crystal/ceramic resonator ext osc (2) 2.ext osc : external osc rc osc (3) 3.rc osc : internal rc oscillator 1111 - 1000 pll output divided by 4 : 16 mhz / pll driven by external crystal/ceramic resonator ext osc ext osc 0100 pll output divided by 4 : 16 mhz / pll driven by external crystal/ceramic resonator pll / 4 ext osc 0101 reserved n/a n/a 0111- 0110 pll output divided by 4 : 16 mhz pll / 4 rc osc 0011 calibrated internal rc oscillator rc osc rc osc 0010 pll output divided by 4 : 16 mhz / pll driven by external clock pll / 4 ext clk (4) 4.ext clk : external clock input 0001 external clock ext clk rc osc 0000 29 4378c?avr?09/08 at90pwm1 frequency of the watchdog oscillator is voltage dependent as shown in ?watchdog oscillator frequency vs. vcc? on page 270 . 7.3 default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is the internal rc oscillator with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. 7.4 low power crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con - figured for use as an on-chip oscillator, as shown in figure 7-2 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillato r, with reduced voltage swing on the xtal2 out - put. it gives the lowest power consumption, but is not capable of driving other clock inputs. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 7-3 . for ceramic resonators, the capacitor values given by the manufacturer should be used. for more information on how to choose capacitors and other details on oscillator operation, refer to the multi-purpose oscillator application note. figure 7-2. crystal oscillator connections the oscillator can operate in three different modes, each optimized for a specific frequency range. the operating mode is selected by the fuses cksel3..1 as shown in table 7-3 . table 7-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 64k (65,536) table 7-3. crystal oscillator operating modes cksel3..1 frequency range (1) (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (2) 0.4 - 0.9 ? xtal2 xtal1 gnd c2 c1 30 4378c?avr?09/08 at90pwm1 notes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 7-4 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ceramic resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 7.5 calibrated internal rc oscillator by default, the internal rc oscillator provides an approximate 8.0 mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 35 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 7-5 . if selected, it will operate with no external components. during reset, hardware loads the pre-programmed calibration value into the osccal register and thereby automatically cal- 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22 table 7-4. start-up times for the oscillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 65 ms ceramic resonator, slowly rising power 010 1k ck (2) 14ck ceramic resonator, bod enabled 011 1k ck (2) 14ck + 4.1 ms ceramic resonator, fast rising power 100 1k ck (2) 14ck + 65 ms ceramic resonator, slowly rising power 1 01 16k ck 14ck crystal oscillator, bod enabled 1 10 16k ck 14ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 14ck + 65 ms crystal oscillator, slowly rising power table 7-3. crystal oscillator operating modes cksel3..1 frequency range (1) (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 31 4378c?avr?09/08 at90pwm1 ibrates the rc oscillator. the accuracy of this calibration is shown as factory calibration in table 23-1 on page 241 . by changing the osccal register from sw, see ?oscillator calibration register ? osccal? on page 31 , it is possible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 23-1 on page 241 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed cali- bration value, see the section ?calibration byte? on page 223 . notes: 1. the device is shipped with this option selected. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. when this oscillator is selected, start-up time s are determined by the sut fuses as shown in table 7-6 on page 31 . note: 1. if the rstdisbl fuse is programmed, this start-up time will be increased to 14ck + 4.1 ms to ensure programming mode can be entered. 2. the device is shipped with this option selected. table 7-7. oscillator calibration register ? osccal ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency. the factory-calibrated value is automat - ically written to this register during chip reset, giving an oscillator frequency of 8.0 mhz at 25c. the application software can write this register to change the oscillator frequency. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz within 1% accuracy. calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and flash write accesses, and these write times will be affected accordingly. if the eeprom or flash are written, do not calibrate to more than 8.8 mhz. otherwise, the eeprom or flash write may fail. table 7-5. internal calibrated rc oscillator operating modes (1)(2) frequency range (mhz) cksel3..0 7.3 - 8.1 0010 table 7-6. start-up times for the internal calibrated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (1) 10 reserved 11 bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value 32 4378c?avr?09/08 at90pwm1 the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two fre - quency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. incrementing cal6..0 by 1 will give a frequency increment of less than 2% in the fre - quency range 7.3 - 8.1 mhz. 7.6 pll to generate high frequency and accurate pwm waveforms, the ?psc?s need high frequency clock input. this clock is generated by a pll. to keep all pwm accuracy, the frequency factor of pll must be configurable by software. with a system clock of 8 mhz, the pll output is 32mhz or 64mhz. 7.6.1 internal pll for psc the internal pll in at90pwm1 generates a clock frequency that is 64x multiplied from nomi - nally 1 mhz input. the source of the 1 mhz pll input clock is the output of the internal rc oscillator which is divided down to 1 mhz. see the figure 7-3 on page 33 . the pll is locked on the rc oscillator and adj usting the rc oscillator via osccal register will adjust the fast peripheral clock at the same time. however, even if the possibly divided rc oscillator is taken to a higher frequency than 1 mhz, the fast peripheral clock frequency satu - rates at 70 mhz (worst case) and remains oscillating at the maximum frequency. it should be noted that the pll in this case is not locked any more with the rc oscillator clock. therefore it is recommended not to take the osccal adjustments to a higher frequency than 1 mhz in order to keep the pll in the correct operating range. the internal pll is enabled only when the plle bit in the register pllcsr is se t. the bit plock from the register pllcsr is set when pll is locked. both internal 1 mhz rc oscillator and pll are switched off in power-down and standby sleep modes . table 7-8. start-up times when the pll is selected as system clock cksel 3..0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) 0011 rc osc 00 1k ck 14ck 01 1k ck 14ck + 4 ms 10 1k ck 14ck + 64 ms 11 16k ck 14ck 0101 ext osc 00 1k ck 14ck 01 1k ck 14ck + 4 ms 10 16k ck 14ck + 4 ms 11 16k ck 14ck + 64 ms 33 4378c?avr?09/08 at90pwm1 figure 7-3. pck clocking system at90pwm2/3 7.6.2 pll control and status register ? pllcsr ? bit 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm1 and always read as zero. ? bit 2 ? pllf: pll factor the pllf bit is used to select the division factor of the pll. if pllf is set, the pll output is 64mhz. if pllf is clear, the pll output is 32mhz. ? bit 1 ? plle: pll enable 0001 ext clk 00 6 ck (1) 14ck 01 6 ck (2) 14ck + 4 ms 10 6 ck (3) 14ck + 64 ms 11 reserved 1. this value do not provide a proper restart ; do not use pd in this clock scheme 2. this value do not provide a proper restart ; do not use pd in this clock scheme 3. this value do not provide a proper restart ; do not use pd in this clock scheme table 7-8. start-up times when the pll is selected as system clock cksel 3..0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) 8 mhz rc oscillator osccal xtal1 xtal2 oscillators divide by 8 divide by 2 ck pll 64x plle lock detector plock source pllf divide by 4 clk pll cksel3..0 bit 76543210 $29 ($29) ? ? ? ? ? pllf plle plock pllcsr read/write r r r r r r/w r/w r initial value 0 0 0 0 0 0 0/1 0 34 4378c?avr?09/08 at90pwm1 when the plle is set, the pll is started and if not yet started the internal rc oscillator is started as pll reference clock. if pll is selected as a system clock source the value for this bit is always 1. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock, and it is safe to enable clk pll for psc. after the pll is enabled, it takes about 100 ms for the pll to lock. 7.7 128 khz internal oscillator the 128 khz internal oscillator is a low power oscillator providing a clock of 128 khz. the fre - quency is nominal at 3v and 25 c. this clock is used by the watchdog oscillator. 7.8 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 7-4 . to run the device on an external clock, the cksel fuses must be programmed to ?0000?. figure 7-4. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses as shown in table 7-10 . when applying an external clock, it is required to avoid sudden changes in the applied clock fre - quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictabl e behavior. it is required to ensure that the mcu is kept in reset during such changes in the clock frequency. table 7-9. external clock frequency cksel3..0 frequency range 0000 0 - 16 mhz table 7-10. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4.1 ms fast rising power 10 6 ck 14ck + 65 ms slowly rising power 11 reserved xtal2 xtal1 gnd nc external clock signal 35 4378c?avr?09/08 at90pwm1 note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. refer to ?system clock prescaler? on page 35 for details. 7.9 clock output buffer when the ckout fuse is programmed, the system clock will be output on clko. this mode is suitable when chip clock is used to drive other ci rcuits on the system. the clock will be output also during reset and the normal operation of i/o pin will be overridden when the fuse is pro - grammed. any clock source, including internal rc oscillator, can be selected when clko serves as clock output. if the system clock prescaler is used, it is the divided system clock that is output (ckout fuse programmed). 7.10 system clock prescaler the at90pwm1 system clock can be divided by setting the clock prescale register ? clkpr. this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 7-11 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corre - sponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu's clock frequency. hence, it is not possible to determine the state of the pre scaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the pre - vious clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 7.10.1 clock prescaler register ? clkpr ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable change of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaniosly written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. bit 7 6543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 36 4378c?avr?09/08 at90pwm1 ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro - nous peripherals is reduced when a division factor is used. the division factors are given in table 7-11 . the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat - ing conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. table 7-11. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 37 4378c?avr?09/08 at90pwm1 8. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump - tion to the application?s requirements. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power-down, power-save, or standby) will be activated by the sleep instruction. see table 3 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and exe - cutes from the reset vector. figure 7-1 on page 27 presents the different clock systems in the at90pwm1, and their distribu - tion. the figure is helpful in selecting an appropriate sleep mode. 8.0.1 sleep mode control register ? smcr the sleep mode control register contains control bits for power management. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 3 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately after waking up. bit 7 6 5 4 3 2 1 0 ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 3. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 reserved 38 4378c?avr?09/08 at90pwm1 8.1 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing spi, usart, analog comparator, adc, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halt clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automati - cally when this mode is entered. 8.2 adc noise reduction mode when the sm2..0 bits are written to 001, t he sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, timer/counter (if their clock source is exte rnal - t0 or t1) and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a timer/counter interrupt, an spm/eeprom ready interrupt, an external level interrupt on int3:0 can wake up the mcu from adc noise reduction mode. 8.3 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external oscillator is stopped, while the external interrupts and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, a psc interrupt, an external level interrupt on int3:0 can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous mod - ules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 74 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 28 . 8.4 standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down 39 4378c?avr?09/08 at90pwm1 with the exception that the oscillator is kept running. from standby mode, the device wakes up in six clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. only level interrupt. 8.5 power reduction register the power reduction register, prr, provides a method to stop the clock to individual peripher - als to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. a full predictible behaviour of a peripheral is not guaranteed during and after a cycle of stopping and starting of its clock. so its recommended to stop a peripheral before stopping its clock with prr register. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consumption. in all other sleep modes, the clock is already stopped. 8.5.1 power reduction register - prr ? bit 7 - prpsc2: power reduction psc2 writing a logic one to this bit reduces the consumption of the psc2 by stopping the clock to this module. when waking up the psc2 again, the psc2 should be re initialized to ensure proper operation. ? bit 6 - prpsc1: power reduction psc1 table 4. active clock domains and wake-up sources in the different sleep modes. active clock domains oscillator s wake-up sources sleep mode clk cpu clk flash clk io clk adc clk pll main clock source enabled int3..0 psc spm/eeprom ready adc wdt otheri/o idle x x x x x x x x x x adc noise reduction xx x x (2) xxxx power- down x (2) xx standby (1) xx (2) x bit 765 4 320 prpsc2 prpsc1 prpsc0 prtim1 prtim0 prspi pradc prr read/write r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 40 4378c?avr?09/08 at90pwm1 writing a logic one to this bit reduces the consumption of the psc1 by stopping the clock to this module. when waking up the psc1 again, the psc1 should be re initialized to ensure proper operation. ? bit 5 - prpsc0: power reduction psc0 writing a logic one to this bit reduces the consumption of the psc0 by stopping the clock to this module. when waking up the psc0 again, the psc0 should be re initialized to ensure proper operation. ? bit 4 - prtim1: power reduction timer/counter1 writing a logic one to this bit reduces the consumption of the timer/counter1 module. when the timer/counter1 is enabled, operation will continue like before the setting of this bit. ? bit 3 - prtim0: power reduction timer/counter0 writing a logic one to this bit reduces the consumption of the timer/counter0 module. when the timer/counter0 is enabled, operation will continue like before the setting of this bit. ? bit 2 - prspi: power reduction serial peripheral interface writing a logic one to this bit reduces the consumption of the serial peripheral interface by stop - ping the clock to this module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit reduces the consumption of the adc by stopping the clock to this module. the adc must be disabled before using this function. the analog comparator cannot use the adc input mux when the clock of adc is stopped. 8.6 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 8.6.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis - abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?cross reference removed? for details on adc operation. 8.6.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 176 for details on how to configure the analog comparator. 8.6.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute sig - 41 4378c?avr?09/08 at90pwm1 nificantly to the total current consumption. refer to ?brown-out detection? on page 45 for details on how to configure the brown-out detector. 8.6.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the adc. if these modul es are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt - age reference? on page 47 for details on the start-up time. 8.6.5 watchdog timer if the watchdog timer is not needed in the applicat ion, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consump - tion. refer to ?watchdog timer? on page 48 for details on how to configure the watchdog timer. 8.6.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?i/o-ports? on page 58 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer s hould be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?digital input disable register 1? didr1? and ?digital input disable register 0 ? didr0? on page 180 and page 199 for details. 8.6.7 on-chip debug system if the on-chip debug system is enabled by ocden fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. in the deeper sleep modes, this will contribute significantly to the total current consumption. 42 4378c?avr?09/08 at90pwm1 9. system control and reset 9.0.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 9-1 shows the reset logic. table 9-1 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif - ferent selections for the delay period are presented in ?clock sources? on page 28 . 9.0.2 reset sources the at90pwm1 has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 43 4378c?avr?09/08 at90pwm1 figure 9-1. reset logic notes: 1. values are guidelines only.. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling) 9.0.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 9-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that th e device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. table 9-1. reset characteristics (1) symbol parameter condition min. typ. max. units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (2) 1.3 2.3 v v rst reset pin threshold voltage 0.2vcc 0.85vcc v t rst minimum pulse width on reset pin 400 ns mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit 44 4378c?avr?09/08 at90pwm1 figure 9-2. mcu start-up, reset tied to v cc figure 9-3. mcu start-up, reset extended externally 9.0.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 9-1 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 9-4. external reset during operation v reset time-out internal reset t tout v pot v rst cc reset time-out internal reset t tout v pot v rst v cc cc 45 4378c?avr?09/08 at90pwm1 9.0.5 brown-out detection at90pwm1 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level dur - ing operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. the test is performed using bodlevel = 010 for low operating voltage and bodlevel = 101 for high operating volt- age . 2. values are guidelines only. notes: 1. values are guidelines only. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 9-5 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 9-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 9-3 . table 9-2. bodlevel fuse coding (1)(2) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 4.5 v 101 2.7 v 100 4.3 v 011 4.4 v 010 4.2 v 001 2.8 v 000 2.6 v table 9-3. brown-out characteristics (1) symbol parameter min. typ. max. units v hyst brown-out detector hysteresis 70 mv t bod min pulse width on brown-out reset 2 s 46 4378c?avr?09/08 at90pwm1 figure 9-5. brown-out reset during operation 9.0.6 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 48 for details on operation of the watchdog timer. figure 9-6. watchdog reset during operation 9.0.7 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag v cc reset time-out internal reset v bot- v bot+ t tout ck cc bit 7 6 5 4 3 2 1 0 ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 47 4378c?avr?09/08 at90pwm1 this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 9.1 internal voltage reference at90pwm1 features an internal bandgap reference. this reference is used for brown-out detection. it can also be used as a voltage reference for the dac and/or the adc, and can be used as analog input for the analog comparators. in order to use the internal vref, it is necessary to configure it thanks to the refs1 and refs0 bits in the admux register and to set an analog feature which requires it. 9.1.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 9-4 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the bodlevel [2..0] fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. 4. when the dac is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc or the dac, the user must always allow the reference to start up before the output from the analog compar - ator or adc or dac is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 9.1.2 voltage reference characteristics note: 1. values are guidelines only. table 9-4. internal voltage reference characteristics (1) symbol parameter condition min. typ. max. units v bg bandgap reference voltage 1.1 v t bg bandgap reference start-up time 40 s i bg bandgap reference current consumption 15 a 48 4378c?avr?09/08 at90pwm1 9.2 watchdog timer at90pwm1 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separate on-chip oscillator ? 3 operating modes ? interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode figure 9-7. watchdog timer the watchdog timer (wdt) is a timer counting cycles of a separate on-chip 128 khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an inter - rupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. the ?watchdog timer always on? (wdton) fuse, if programmed, will force the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and inter - rupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follo w timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. 128 khz oscillator mcu reset interrupt wdie wdif osc/2k osc/4k osc/8k wdp3 49 4378c?avr?09/08 at90pwm1 the following code example shows one assembly and one c function for turning off the watch - dog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. note: 1. the example code assumes that the part specific header file is included. note: if the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialisation routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 52 4378c?avr?09/08 at90pwm1 . table 9-6. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 53 4378c?avr?09/08 at90pwm1 10. interrupts this section describes the specifics of the interrupt handling as performed in at90pwm1. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 14 . 10.1 interrupt vectors in at90pwm1 table 5. reset and interrupt vectors vector no. program address source interrupt definition 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset, and emulation avr reset 2 0x0001 psc2 capt psc2 capture event 3 0x0002 psc2 ec psc2 end cycle 4 0x0003 psc1 capt psc1 capture event 5 0x0004 psc1 ec psc1 end cycle 6 0x0005 psc0 capt psc0 capture event 7 0x0006 psc0 ec psc0 end cycle 8 0x0007 anacomp 0 analog comparator 0 9 0x0008 anacomp 1 analog comparator 1 10 0x0009 anacomp 2 analog comparator 2 11 0x000a int0 external interrupt request 0 12 0x000b timer1 capt timer/counter1 capture event 13 0x000c timer1 compa timer/counter1 compare match a 14 0x000d timer1 compb timer/counter1 compare match b 15 0x000e 16 0x000f timer1 ovf timer/counter1 overflow 17 0x0010 timer0 compa timer/counter0 compare match a 18 0x0011 timer0 ovf timer/counter0 overflow 19 0x0012 adc adc conversion complete 20 0x0013 int1 external interrupt request 1 21 0x0014 spi, stc spi serial transfer complete 22 0x0015 23 0x0016 24 0x0017 25 0x0018 int2 external interrupt request 2 26 0x0019 wdt watchdog time-out interrupt 27 0x001a ee ready eeprom ready 28 0x001b timer0 compb timer/counter0 compare match b 54 4378c?avr?09/08 at90pwm1 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 205 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 6 shows reset and interrupt vectors placement for the various combinations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 70 on page 218 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in at90pwm1 is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp psc2_capt ; psc2 capture event handler 0x002 rjmp psc2_ec ; psc2 end cycle handler 0x003 rjmp psc1_capt ; psc1 capture event handler 0x004 rjmp psc1_ec ; psc1 end cycle handler 0x005 rjmp psc0_capt ; psc0 capture event handler 0x006 rjmp psc0_ec ; psc0 end cycle handler 0x007 rjmp ana_comp_0 ; analog comparator 0 handler 0x008 rjmp ana_comp_1 ; analog comparator 1 handler 0x009 rjmp ana_comp_2 ; analog comparator 2 handler 0x00a rjmp ext_int0 ; irq0 handler 0x00b rjmp tim1_capt ; timer1 capture handler 0x00c rjmp tim1_compa ; timer1 compare a handler 0x00d rjmp tim1_compb ; timer1 compare b handler 0x00f rjmp tim1_ovf ; timer1 overflow handler 29 0x001c int3 external interrupt request 3 30 0x001d 31 0x001e 32 0x001f spm ready store program memory ready table 6. reset and interrupt vectors placement in at90pwm1 (1) bootrst ivsel reset address interrupt vectors start address 1 0 0x000 0x001 1 1 0x000 boot reset address + 0x001 0 0 boot reset address 0x001 0 1 boot reset address boot reset address + 0x001 table 5. reset and interrupt vectors vector no. program address source interrupt definition 55 4378c?avr?09/08 at90pwm1 0x010 rjmp tim0_compa ; timer0 compare a handler 0x011 rjmp tim0_ovf ; timer0 overflow handler 0x012 rjmp adc ; adc conversion complete handler 0x013 rjmp ext_int1 ; irq1 handler 0x014 rjmp spi_stc ; spi transfer complete handler 0x018 rjmp ext_int2 ; irq2 handler 0x019 rjmp wdt ; watchdog timer handler 0x01a rjmp ee_rdy ; eeprom ready handler 0x01b rjmp tim0_compb ; timer0 compare b handler 0x01c rjmp ext_int3 ; irq3 handler 0x01f rjmp spm_rdy ; store program memory ready handler ; 0x020reset: ldi r16, high(ramend); main program start 0x021 out sph,r16 ; set stack pointer to top of ram 0x022 ldi r16, low(ramend) 0x023 out spl,r16 0x024 sei ; enable interrupts 0x025 56 4378c?avr?09/08 at90pwm1 0xc01 out sph,r16 ; set stack pointer to top of ram 0xc02 ldi r16,low(ramend) 0xc03 out spl,r16 0xc04 sei ; enable interrupts 0xc05 57 4378c?avr?09/08 at90pwm1 ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing from the application section. if interrupt vectors are placed in the application section and boot lock bit blb12 is programed, interrupts are dis- abled while executing from the boot loader section. refer to the section ?boot loader support ? read-while-write self-programming? on page 205 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is written or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description above. see code example below. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 59 4378c?avr?09/08 at90pwm1 11.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 11-2 shows a func - tional description of one i/o-port pin, here generically called pxn. figure 11-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 11.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o-ports? on page 72 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 60 4378c?avr?09/08 at90pwm1 if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 11.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 11.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully accept - able, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 7 summarizes the control signals for the pin value. 11.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 11-2 , the pinxn register bit and the preceding latch con - stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 11-3 shows a timing dia - gram of the synchronization when reading an ex ternally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 7. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 61 4378c?avr?09/08 at90pwm1 figure 11-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows t pd,max and t pd,min , a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi - cated in figure 11-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay t pd through the synchronizer is 1 system clock period. figure 11-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 62 4378c?avr?09/08 at90pwm1 values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 11.2.5 digital input enable and sleep modes as shown in figure 11-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the fi gure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrupt pins. if the external interrupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in ?alternate port functions? on page 63 . if a logic high level (?one?) is present on an a synchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. table 2. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 64 4378c?avr?09/08 at90pwm1 the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 8. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 65 4378c?avr?09/08 at90pwm1 11.3.1 mcu control register ? mcucr ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). se 11.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 9 . the alternate pin configuration is as follows: ? pscout01/adc4/sck ? bit 7 pscout01: output 1 of psc 0. adc4, analog to digital converter, input channel 4 . sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb7. when the spi is enabled as a master, the data direction of this pin is controlled by ddb7. when the pin is forced to be an input, the pull-up can still be controlled by the portb7 bit. ? adc7/icp1b/pscout11 ? bit 6 adc7, analog to digital converter, input channel 7 . icp1b, input capture pin: the pb6 pin can act as an input capture pin for timer/counter1. pscout11: output 1 of psc 1. bit 7 6 5 4 3 2 1 0 spips ? ?pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 9. port b pins alternate functions port pin alternate functions pb7 pscout01 output adc4 (analog input channel 4) sck (spi bus serial clock) pb6 adc7 (analog input channel 7) icp1b (timer 1 input capture alternate input) pscout11 output (see note 4) pb5 adc6 (analog input channel 6) int2 pb4 amp0+ (analog differential amplifier 0 input channel ) pb3 amp0- (analog differential amplifier 0 input channel ) pb2 adc5 (analog input channel5 ) int1 pb1 mosi (spi master out slave in) pscout21 output pb0 miso (spi master in slave out) pscout20 output 66 4378c?avr?09/08 at90pwm1 ? adc6/int2 ? bit 5 adc6, analog to digital converter, input channel 6 . int2, external interrupt source 2. this pin can serve as an external interrupt source to the mcu. ? apm0+ ? bit 4 amp0+, analog differential amplifier 0 positive input channel. ? amp0- ? bit 3 amp0-, analog differential amplifier 0 negative input channel. ? adc5/int1 ? bit 2 adc5, analog to digital converter, input channel 5 . int1, external interrupt source 1. this pin can serve as an external interrupt source to the mcu. ? mosi/pscout21 ? bit 1 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1 when the spi is enabled as a master, the data direction of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up can still be controlled by the portb1 and pud bits. pscout21: output 1 of psc 2. ?miso/psc20 ? bit 0 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb0. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 and pud bits. pscout20: output 0 of psc 2. 67 4378c?avr?09/08 at90pwm1 table 10 and table 11 relates the alternate functions of port b to the overriding signals shown in figure 11-5 on page 63 . table 10. overriding signals for alternate functions in pb7..pb4 signal name pb7/adc4/ pscout01/sck pb6/adc7/ pscout11/ icp1b pb5/adc6/ int2 pb4/amp0+ puoe spe ? mstr ? spips 000 puov pb7 ? pud ? spips 000 ddoe spe ? mstr ? spips + pscen01 pscen11 0 0 ddov pscen01 1 0 0 pvoe spe ? mstr ? spips pscen11 0 0 pvov pscout01 ? spips + pscout01 ? pscen01 ? spips + pscout01 ? pscen01 ? spips pscout11 0 0 dieoe adc4d adc7d adc6d + in2en amp0nd dieov 0 0 in2en 0 di sckin ? spips ? ireset icp1b int2 aio adc4 adc7 adc6 amp0+ table 11. overriding signals for alternate functions in pb3..pb0 signal name pb3/amp0- pb2/adc5/int1 pb1/mosi/ pscout21 pb0/miso/ pscout20 puoe00?? puov00?? ddoe00?? ddov00?? pvoe00?? pvov00?? dieoe amp0nd adc5d + in1en 0 0 dieov 0 in1en 0 0 di int1 mosi_in ? spips ? ireset miso_in ? spips ? ireset aio amp0- adc5 ? ? 68 4378c?avr?09/08 at90pwm1 11.3.3 alternate functions of port d the port d pins with alternate functions are shown in table 12 . the alternate pin configuration is as follows: ? acmp0 ? bit 7 acmp0, analog comparator 0 positive input. conf igure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana - log comparator. ? adc3/acmpm/int0 ? bit 6 adc3, analog to digital converter, input channel 3. acmpm, analog comparators negative input. config ure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana - log comparator. int0, external interrupt source 0. this pin can serve as an external interrupt source to the mcu. ? adc2/acmp2 ? bit 5 adc2, analog to digital converter, input channel 2. acmp2, analog comparator 1 positive input. conf igure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana - log comparator. ? adc1/icp1/sck_a ? bit 4 adc1, analog to digital converter, input channel 1. table 12. port d pins alternate functions port pin alternate function pd7 acmp0 (analog comparator 0 positive input ) pd6 adc3 (analog input channel 3 ) acmpm reference for analog comparators int0 pd5 adc2 (analog input channel 2) acmp2 (analog comparator 2 positive input ) pd4 adc1 (analog input channel 1) icp1 (timer 1 input capture) sck_a (programming & alternate spi clock) pd3 oc0a (timer 0 output compare a) ss (spi slave select) mosi_a (programming & alternate spi master out slave in) pd2 pscin2 (psc 2 digital input) oc1a (timer 1 output compare a) miso_a (programming & alternate master in spi slave out) pd1 pscin0 (psc 0 digital input ) clko (system clock output) pd0 pscout00 output ss_a (alternate spi slave select) 69 4378c?avr?09/08 at90pwm1 icp1 ? input capture pin1: this pin can act as an input capture pin for timer/counter1. sck_a: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd4. when the spi is enabled as a master, the data direction of this pin is controlled by ddd4. when the pin is forced to be an input, the pull-up can still be controlled by the portd4 bit. ? oc0a/ss/mosi_a, bit 3 oc0a, output compare match a output: this pin can serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddd3 set ?one?) to serve this function. the oc0a pin is also the output pin for the pwm mode ss : slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd3. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddd3. when the pin is forced to be an input, the pull-up can still be controlled by the portd3 bit. mosi_a: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd3 when the spi is enabled as a master, the data direction of this pin is controlled by ddd3. when the pin is forced to be an input, the pull-up can still be controlled by the portd3 bit. ? pscin2/oc1a/miso_a, bit 2 pcsin2, psc 2 digital input. oc1a, output compare match a output: this pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddd2 set ?one?) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. miso_a: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddd2. when the spi is enabled as a slave, the data direction of this pin is controlled by ddd2. when the pin is forced to be an input, the pull-up can still be controlled by the portd2 bit. ? pscin0/clko ? bit 1 pcsin0, psc 0 digital input. clko, divided system clock: the divided system clock can be output on this pin. the divided system clock will be output if the ckout fuse is programmed, regardless of the portd1 and ddd1 settings. it will also be output during reset. ? pscout00/ss_a ? bit 0 pscout00: output 0 of psc 0. ss _a: slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddd0. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddd0. when the pin is forced to be an input, the pull-up can still be controlled by the portd0 bit. 70 4378c?avr?09/08 at90pwm1 table 13 and table 14 relates the alternate functions of port d to the overriding signals shown in figure 11-5 on page 63 . table 13. overriding signals for alternate functions pd7..pd4 signal name pd7/ acmp0 pd6/adc3/ acmpm/int0 pd5/adc2/ acmp2 pd4/adc1/ icp1a/sck_a puoe 0 0 0 spe ? mstr ? spips puov 0 0 0 pd4 ? pud ddoe 0 0 0 spe ? mstr ? spips ddov 0 0 0 0 pvoe 0 0 0 spe ? mstr ? spips pvov 0 0 0 ? dieoe acmp0d adc3d + in0en adc2d adc1d dieov 0 in0en 0 0 di ? int0 icp1a aio acomp0 adc3 acmpm adc2 acomp2 adc1 71 4378c?avr?09/08 at90pwm1 11.3.4 alternate functions of port e the port e pins with alternate functions are shown in table 15 . the alternate pin configuration is as follows: ? xtal2/adc0 ? bit 2 xtal2: chip clock oscillator pin 2. used as clock pin for crystal oscillator or low-frequency crystal oscillator. when used as a clock pin, the pin can not be used as an i/o pin. adc0, analog to digital converter, input channel 0. ? xtal1/oc0b ? bit 1 table 14. overriding signals for alternate functions in pd3..pd0 signal name pd3/oc0a/ ss/mosi_a pd2/pscin2/ oc1a/miso_a pd1/pscin0/ clko pd0/pscout00/ ss_a puoe spe ? mstr ? spips ?0 spe ? mstr ? spips puov spe ? mstr ? spips ? pd3 ? pud ? 0 pd0 ? pud ddoe spe ? mstr ? spips ?0 pscen00 + spe ? mstr ? spips ddov 0 0 pscen00 pvoe oc0en + spe ? mstr ? spips ? 0 pscen00 + umsel pvov txd + txen ? (oc0en ? oc0 + oc0en ? spips ? mosi) ?0? dieoe 0 0 0 0 dieov 0 0 0 0 di ss mosi_ain ss_a aio table 15. port e pins alternate functions port pin alternate function pe2 xtal2: xtal output adc0 (analog input channel 0) pe1 xtal1: xtal input oc0b (timer 0 output compare b) pe0 reset# (reset input) ocd (on chip debug i/o) 72 4378c?avr?09/08 at90pwm1 xtal1: chip clock oscillator pin 1. used for all chip clock sources except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. oc0b, output compare match b output: this pin can serve as an external output for the timer/counter0 output compare b. the pin has to be configured as an output (dde1 set ?one?) to serve this function. this pin is also the output pin for the pwm mode timer function. ? reset /ocd ? bit 0 reset , reset pin: when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to rely on power-on reset and brown-out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pe0 is used as a reset pin, dde0, porte0 and pine0 will all read 0. table 16 relates the alternate functions of port e to the overriding signals shown in figure 11-5 on page 63 . 11.4 register description for i/o-ports 11.4.1 port b data register ? portb 11.4.2 port b data direction register ? ddrb table 16. overriding signals for alternate functions in pe2..pe0 signal name pe2/adc0/ xtal2 pe1/oc0b pe0/reset / ocd puoe 0 0 0 puov 0 0 0 ddoe 0 0 0 ddov 0 0 0 pvoe 0 oc0ben 0 pvov 0 oc0b 0 dieoe adc0d 0 0 dieov 0 0 0 di aio osc output adc0 osc / clock input bit 76543210 portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w 73 4378c?avr?09/08 at90pwm1 11.4.3 port b input pins address ? pinb 11.4.4 port d data register ? portd 11.4.5 port d data direction register ? ddrd 11.4.6 port d input pins address ? pind 11.4.7 port e data register ? porte 11.4.8 port e data direction register ? ddre 11.4.9 port e input pins address ? pine initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 port d3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? ? ? ? ? porte2 porte1 porte0 porte read/write r r r r r r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? ? dde2 dde1 dde0 ddre read/write r r r r r r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? ? pine2 pine1 pine0 pine read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 n/a n/a n/a 74 4378c?avr?09/08 at90pwm1 12. external interrupts the external interrupts are triggered by the int3:0 pins. observe that, if enabled, the interrupts will trigger even if the int3:0 pins are configured as outputs. this feature provides a way of gen - erating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control reg - isters ? eicra (int3:0). when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int3:0 requires the presence of an i/o clock, described in ?clock sys - tems and their distribution? on page 27 . the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. this makes the mcu less sensitive to noise. the changed level is sampled twice by the watchdog oscillator clock. the period of the watchdog oscillator is 1 s (nominal) at 5.0v and 25 c. the frequency of the watchdog oscilla - tor is voltage dependent as shown in the ?electrical characteristics(1)? on page 238 . the mcu will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. the start-up time is defined by the sut fuses as described in ?system clock? on page 27 . if the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the mcu will still wake up, but no interrupt will be generated. the required level must be held long enough for the mcu to complete the wake up to trigger the level interrupt. 12.0.1 external interrupt control register a ? eicra ? bits 7..0 ? isc31, isc30 ? isc01, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 17 . edges on int3..int0 are registered asynchro - nously.the value on the int3:0 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longe r than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 17. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge between two samples of intn generates an interrupt request. 1 1 the rising edge between two samples of intn generates an interrupt request. 75 4378c?avr?09/08 at90pwm1 note: 1. n = 3, 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 12.0.2 external interrupt mask register ? eimsk ? bits 3..0 ? int3 ? int0: external interrupt request 3 - 0 enable when an int3 ? int0 bit is written to one and t he i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control register ? eicra ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 12.0.3 external interrupt flag register ? eifr ? bits 3..0 ? intf3 - intf0: external interrupt flags 3 - 0 when an edge or logic change on the int3:0 pin triggers an interrupt request, intf3:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int3:0 in eimsk, are set (one), the mcu will jump to the interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int3:0 are configured as level interrupt. bit 76543210 - - - - int3 int2 int1 iint0 eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - - - intf3 intf2 intf1 iintf0 eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 76 4378c?avr?09/08 at90pwm1 13. timer/counter0 and timer/counter1 prescalers timer/counter1 and timer/counter0 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 13.0.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 13.0.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu - tion. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 13.0.3 external clock source an external clock source applied to the tn /t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the tn/t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 13-1 shows a functional equivalent block diagram of the tn/t0 synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 13-1. tn/t0 pin sampling the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn/t0 pin to the counter is updated. enabling and disabling of the clock input must be done when tn/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 77 4378c?avr?09/08 at90pwm1 each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys - tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre - quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal , resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 13-2. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( tn/t0) is shown in figure 13-1 . 13.0.4 general timer/counter control register ? gtccr ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psrsync bit is kept, hence keeping the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. when the tsm bit is written to zero, the psrsync bit is cleared by hardware, and the timer/counters start counting simultaneously. ? bit6 ? icpsel1: timer 1 input capture selection psrsync clear clk t1 clk t0 t1 t0 clk i/o synchronization synchronization bit 7654321 0 tsm icpsel1 ? ? ? ? ? psrsync gtccr read/write r/w r/w r r r r r r/w initial value 0 0 0 0 0 0 0 0 78 4378c?avr?09/08 at90pwm1 timer 1 capture function has two possible inputs icp1a (pd4) and icp1b (pb6). the selection is made thanks to icpsel1 bit as described in table . ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/counter1 and timer/counter0 prescaler will be reset. this bit is nor - mally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. table 18. icpsel1 icpsel1 description 0 select icp1a as trigger for timer 1 input capture 1 select icp1b as trigger for timer 1 input capture 79 4378c?avr?09/08 at90pwm1 14. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bit timer/counter module, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event man - agement) and wave generation. the main features are: ? two independent output compare units ? double buffered output compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 14.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 14-1 . for the actual placement of i/o pins, refer to ?pin descriptions? on page 7 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca - tions are listed in the ?8-bit timer/counter register description? on page 89 . the prtim0 bit in ?power reduction register? on page 39 must be written to zero to enable timer/counter0 module. figure 14-1. 8-bit timer/counter block diagram 14.1.1 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com - pare unit, in this case compare unit a or compare unit b. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. timer/counter data b u s = tcntn waveform generation ocna control logic count clear direction tovn (int.req.) ocrnx tccrna clock select tn edge detector ( from prescaler ) clk tn ocna (int.req.) = ocrnx waveform generation ocnb ocnb (int.req.) tccrnb = fixed top values = 0 top bottom 80 4378c?avr?09/08 at90pwm1 the definitions in table 19 are also used extensively throughout the document. 14.1.2 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all interrupts are individually masked with the timer inter - rupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen - erator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). see ?using the output compare unit? on page 106. for details. the compare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an out - put compare interrupt request. 14.2 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0b). for details on clock sources and pres - caler, see ?timer/counter0 and timer/counter1 prescalers? on page 76 . 14.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 14-2 shows a block diagram of the counter and its surroundings. figure 14-2. counter unit block diagram signal description (internal signals): table 19. definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 81 4378c?avr?09/08 at90pwm1 count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has reached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 84 . the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 14.4 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare flag (ocf0a or ocf0b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is exe - cuted. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 84 ). figure 14-3 shows a block diagram of the output compare unit. 82 4378c?avr?09/08 at90pwm1 figure 14-3. output compare unit, block diagram the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the dou - ble buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is dis - abled the cpu will access the ocr0x directly. 14.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. forcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings define whether the oc0x pin is set, cleared or toggled). 14.4.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initial - ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 14.4.3 using the output compare unit since writing tcnt0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 83 4378c?avr?09/08 at90pwm1 the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output com - pare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x1:0 bits are not double buffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 14.5 compare match output unit the compare output mode (com0x1:0) bits have two functions. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 14-4 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 14-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direction (input or out - put) is still controlled by the data direction regi ster (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visi - ble on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the out - put is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 89. 14.5.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focn clk i/o 84 4378c?avr?09/08 at90pwm1 non-pwm modes refer to table 20 on page 90 . for fast pwm mode, refer to table 21 on page 90 , and for phase correct pwm refer to table 22 on page 90 . a change of the com0x1:0 bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc0x strobe bits. 14.6 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm out - put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 83. ). for detailed timing information refer to ?timer/counter timing diagrams? on page 88 . 14.6.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot - tom (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. howe ver, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out - put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 14.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 14-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. 85 4378c?avr?09/08 at90pwm1 figure 14-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is run - ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 14.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high fre - quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot - tom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the out - put is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 14-6 . the tcnt0 value is in the timing diagram shown as a his - togram for illustrating the single-slope operation. the diagram includes non-inverted and t cntn o cn ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 86 4378c?avr?09/08 at90pwm1 inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 14-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the inter - rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 24 on page 91 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set - ting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the out - put compare unit is enabled in the fast pwm mode. tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocn ocn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 87 4378c?avr?09/08 at90pwm1 14.6.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot - tom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcount - ing. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmet - ric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 14-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 14-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 25 on page 91 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 88 4378c?avr?09/08 at90pwm1 match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 14-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot - tom. there are two cases that give a transition without compare match. ? ocrnx changes its value from max, like in figure 14-7 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at max must correspond to the result of an up- counting compare match. ? the timer starts counting from a value higher than the one in ocrnx, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. 14.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 14-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 14-8. timer/counter timing diagram, no prescaling figure 14-9 shows the same timing data, but with the prescaler enabled. f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 89 4378c?avr?09/08 at90pwm1 figure 14-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 14-10 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 14-10. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 14-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 14-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 14.8 8-bit timer/counter register description 14.8.1 timer/counter control register a ? tccr0a tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 90 4378c?avr?09/08 at90pwm1 ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 20 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 21 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 85 for more details. table 22 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 111 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode table 20. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 21. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at top 1 1 set oc0a on compare match, clear oc0a at top table 22. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. 91 4378c?avr?09/08 at90pwm1 these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 23 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 24 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 85 for more details. table 25 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 87 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode table 23. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 24. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match, set oc0b at top 1 1 set oc0b on compare match, clear oc0b at top table 25. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. 92 4378c?avr?09/08 at90pwm1 combined with the wgm02 bit found in the tccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of wave - form generation to be used, see table 26 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 84 ). notes: 1. max = 0xff 2. bottom = 0x00 14.8.2 timer/counter control register b ? tccr0b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a table 26. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/count er mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3011fast pwm0xfftopmax 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7111fast pwmocratoptop bit 7 6 5 4 3 2 1 0 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 93 4378c?avr?09/08 at90pwm1 strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?timer/counter control register a ? tccr0a? on page 89 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. if external pin modes are used for the timer/coun ter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 14.8.3 timer/counter register ? tcnt0 the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 14.8.4 output compare register a ? ocr0a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. table 27. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 94 4378c?avr?09/08 at90pwm1 14.8.5 output compare register b ? ocr0b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. 14.8.6 timer/counter interrupt mask register ? timsk0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and t he i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 inter - rupt flag register ? tifr0. 14.8.7 timer/counter 0 interrupt flag register ? tifr0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the cor - responding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag bit 76543210 ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 10 ? ? ? ? ? ocie0b ocie0a toie0 timsk0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ?????ocf0bocf0atov0tifr0 read/write r r r r r r/w r/w r/w initial value00000000 95 4378c?avr?09/08 at90pwm1 the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the cor - responding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (t imer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 26 , ?waveform generation mode bit description? on page 92 . 96 4378c?avr?09/08 at90pwm1 15. 16-bit timer/counter1 with pwm the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. the main features are: ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 15.1 overview most register and bit references in this sect ion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 15-1 . for the actual placement of i/o pins, refer to ?pin descriptions? on page 4 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca - tions are listed in the ?16-bit timer/counter register description? on page 116 . the prtim1 bit in ?power reduction register? on page 39 must be written to zero to enable timer/counter1 module. 97 4378c?avr?09/08 at90pwm1 figure 15-1. 16-bit timer/counter block diagram (1) note: 1. refer to table on page 4 for timer/counter1 pin placement and description. 15.1.1 registers the timer/counter (tcntn), output compare registers (ocrnx), and input capture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 98 . the timer/counter control registers (tccrnx) are 8-bit register s and have no cpu access restrictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifrn). all interrupts are individually masked with the timer inter - rupt mask register (timskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrnx) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (ocnx). see ?output compare units? on page 104. the compare match event will also set the compare match flag (ocfnx) which can be used to generate an output compare interrupt request. clock select timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpnb = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn icpna icpsel1 0 1 98 4378c?avr?09/08 at90pwm1 the input capture register can capture the timer/counter value at a given external (edge trig - gered) event on either the input capture pin (icpn). the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna register can not be used for generating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 15.1.2 definitions the following definitions are used extensively throughout the section: 15.2 accessing 16-bit registers the tcntn, ocrnx, and icrn are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the tempo - rary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocrnx 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrnx and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. table 28. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocrna or icrn register. the assignment is dependent of the mode of operation. 99 4378c?avr?09/08 at90pwm1 note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis - ters, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. table 3. assembly code examples (1) ... ; set tcnt n to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt n h,r17 out tcnt n l,r16 ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ... c code examples (1) unsigned int i; ... /* set tcnt n to 0x01ff */ tcnt n = 0x1ff; /* read tcnt n into i */ i = tcnt n ; ... 100 4378c?avr?09/08 at90pwm1 the following code examples show how to do an atomic read of the tcntn register contents. reading any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. table 4. assembly code example (1) tim16_readtcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt n ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt n into i */ i = tcnt n ; /* restore global interrupt flag */ sreg = sreg; return i; } 101 4378c?avr?09/08 at90pwm1 the following code examples show how to do an atomic write of the tcntn register contents. writing any of the ocrnx or icrn registers can be done by using the same principle. note: 1. the example code assumes that the part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be writ - ten to tcntn. 15.2.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 15.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 76 . table 5. assembly code example (1) tim16_writetcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt n to r17:r16 out tcnt n h,r17 out tcnt n l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt n ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt n to i */ tcnt n = i; /* restore global interrupt flag */ sreg = sreg; } 102 4378c?avr?09/08 at90pwm1 15.4 counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 15-2 shows a block diagram of the counter and its surroundings. figure 15-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcntnh) con - taining the upper eight bits of the counter, and counter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirectly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register value when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcntn register when the counter is counting that will give unpredictable results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, independent of whether clk t n is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs ocnx. for more details about advanced counting sequences and waveform generation, see ?16-bit timer/counter1 with pwm? on page 96 . the timer/counter overflow flag (tovn) is set according to the mode of operation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 103 4378c?avr?09/08 at90pwm1 15.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul - tiple events, can be applied via the icpn pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig - nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 15-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 15-3. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a capture is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copied into icrn register. if enabled (icien = 1), the input capture flag generates an input capture interrupt. the icfn flag is automatically cleared when the interrupt is executed. alternativ ely the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). when the low byte is read the high byte is copied into the high byte temporary register (temp). when the cpu reads the icrnh i/o location it will access the temp register. the icrn register can only be written when us ing a waveform generation mode that utilizes the icrn register for defining the counter?s top value. in these cases the waveform genera - tion mode (wgmn3:0) bits must be set before the top value can be written to the icrn register. when writing the icrn register the high byte must be written to the icrnh i/o location before the low byte is written to icrnl. icfn (int.req.) write icrn (16-bit register) icrnh (8-bit) noise canceler icpnb edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icpsel1 icnc ices icpna 104 4378c?avr?09/08 at90pwm1 for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 98 . 15.5.1 input capture trigger source the trigger sources for the input capture unit arethe input capture pin (icp1a & icp1b). be aware that changing trigger source can trigger a capture. the input capture flag must there - fore be cleared after the change. the input capture pin (icpn) is sampled using the same technique as for the tn pin ( figure 13- 1 on page 76 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icrn to define top. an input capture can be triggered by software by controlling the port of the icpn pin. 15.5.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler introduces addi - tional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the syst em clock and is therefore not affected by the prescaler. 15.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icrn register before the next event occurs, the icrn will be overwritten with a new value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the inter - rupt handler routine as possible. even though th e input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle re quires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if an interrupt handler is used). 15.6 output compare units the 16-bit comparator continuously compares tcntn with the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next ?timer clock cycle?. if enabled (ocienx = 1), the output com - pare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is executed. alternatively the ocfnx flag can be cleared by software by writ - 105 4378c?avr?09/08 at90pwm1 ing a logical one to its i/o bit location. the wa veform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?16-bit timer/counter1 with pwm? on page 96. ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 15-4 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = n for timer/counter n), and the ?x? indicates output compare unit (x). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 15-4. output compare unit, block diagram the ocrnx register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocrnx com - pare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out - put glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is dis - abled the cpu will access the ocrnx directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocrnx registers must be done via the temp reg - ister since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data b u s (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 106 4378c?avr?09/08 at90pwm1 updated by the value written. then when the low byte (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 98 . 15.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forcing compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real compare match had occurred (the comn1:0 bits settings define whether the ocnx pin is set, cleared or toggled). 15.6.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tcntn without triggering an interrupt when the timer/counter clock is enabled. 15.6.3 using the output compare unit since writing tcntn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the compare match will be missed, resulting in incorrect wave - form generation. do not write the tcntn equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. similarly, do not write the tcntn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output com - pare (focnx) strobe bits in normal mode. the ocnx register keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not double buffered together with the compare value. changing the comnx1:0 bits will take effect immediately. 15.7 compare match output unit the compare output mode (comnx1:0) bits have two functions. the waveform generator uses the comnx1:0 bits for defining the output compare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. figure 15-5 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. when referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. 107 4378c?avr?09/08 at90pwm1 figure 15-5. compare match output unit, schematic the general i/o port function is overridden by the output compare (ocnx) from the waveform generator if either of the comnx1:0 bits are set. however, the ocnx pin direction (input or out - put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be set as output before the ocnx value is visi - ble on the pin. the port override function is generally independent of the waveform generation mode, but there are some exceptions. refer to table 29 , table 30 and table 31 for details. the design of the output compare pin logic allows initialization of the ocnx state before the out - put is enabled. note that some comnx1:0 bit settings are reserved for certain modes of operation. see ?16-bit timer/counter register description? on page 116. the comnx1:0 bits have no effect on the input capture unit. 15.7.1 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the waveform generator that no action on the ocnx register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 29 on page 117 . for fast pwm mode refer to table 30 on page 117 , and for phase correct and phase and frequency correct pwm refer to table 31 on page 117 . a change of the comnx1:0 bits state will have effect at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the focnx strobe bits. 15.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the comnx1:0 bits control whether the pwm out - port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 108 4378c?avr?09/08 at90pwm1 put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 106. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 115 . 15.8.1 normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn becomes zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by soft - ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 15.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the opera - tion of counting external events. the timing diagram for the ctc mode is shown in figure 15-6 . the counter value (tcntn) increases until a compare match occurs with either ocrna or icrn, and then counter (tcntn) is cleared. figure 15-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if the tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) 109 4378c?avr?09/08 at90pwm1 interrupt is enabled, the interrupt handler routine can be used for updating the top value. how - ever, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buff - ering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the compare match. the counter will then have to count to its max - imum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocrna then will be double buffered. for generating a waveform output in ctc mode, the ocna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). the waveform generated will have a maximum fre - quency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 15.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compare match between tcntn and ocrnx, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope oper - ation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre - quency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically sm all sized external components (coils, capaci - tors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the max - imum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 15-7 . the figure shows fast pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = r fpwm top 1 + () log 2 () log ---------------------------------- - = 110 4378c?avr?09/08 at90pwm1 figure 15-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer clock cycle as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt han - dler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icrn value written is lower than the current value of tcntn. the result will then be that the counter will miss the compare match at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcntn matches top. the update is done at the same timer clock cycle as the tcntn is cleared and the tovn flag is set. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively changed (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 117 ). the actual ocnx value will only be visible on the port pin if the dat a direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 111 4378c?avr?09/08 at90pwm1 the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the out - put will be a narrow spike for each top+1 timer clock cycle. setting the ocrnx equal to top will result in a constant high or low output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set - ting ocna to toggle its logical level on each compare match (comna1:0 = 1). this applies only if ocr1a is used to define the top value (wgm13:0 = 15). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output com - pare unit is enabled in the fast pwm mode. 15.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu - tion in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 15-8 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx inter - rupt flag will be set when a compare match occurs. f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = r pcpwm top 1 + () log 2 () log ---------------------------------- - = 112 4378c?avr?09/08 at90pwm1 figure 15-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches bottom. when either ocrna or icrn is used for defining the top value, the ocna or icfn flag is set accord - ingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values, the unused bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 15-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx reg - ister. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 117 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx regis - ter at the compare match between ocrnx and tcntn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 113 4378c?avr?09/08 at90pwm1 the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 15.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high resolution phase and frequency correct pwm wave - form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre - quency compared to the single-slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is updated by the ocrnx buffer register, (see figure 15- 8 and figure 15-9 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 15-9 . the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing dia - gram shown as a histogram for illustrating the dual-slope operation. the diagram includes non- inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes repre - sent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 114 4378c?avr?09/08 at90pwm1 figure 15-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. as figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri - cal in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. however, if the base pwm frequency is actively changed by changing the top value, using the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm wave - forms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 117 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter incre - ments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = 115 4378c?avr?09/08 at90pwm1 the extreme values for the ocrnx register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non- inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 15.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocrnx register is updated with the ocrnx buffer value (only for modes utilizing double buffering). figure 15-10 shows a timing diagram for the setting of ocfnx. figure 15-10. timer/counter timing diagram, setting of ocfnx, no prescaling figure 15-11 shows the same timing data, but with the prescaler enabled. figure 15-11. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 15-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 116 4378c?avr?09/08 at90pwm1 figure 15-12. timer/counter timing diagram, no prescaling figure 15-13 shows the same timing data, but with the prescaler enabled. figure 15-13. timer/counter timing diagram, with prescaler (f clk_i/o /8) 15.10 16-bit timer/counter register description 15.10.1 timer/counter1 control register a ? tccr1a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b the comna1:0 and comnb1:0 control the output compare pins (ocna and ocnb respec - tively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bit are written to one, the ocnb output overrides the normal port functionality of the tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value00000000 117 4378c?avr?09/08 at90pwm1 i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond - ing to the ocna or ocnb pin must be set in order to enable the output driver. when the ocna or ocnb is connected to the pin, the function of the comnx1:0 bits is depen - dent of the wgmn3:0 bits setting. table 29 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). table 30 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 109. for more details. table 31 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the phase cor - rect or the phase and frequency correct, pwm mode. table 29. compare output mode, non-pwm comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 0 1 toggle ocna/ocnb on compare match. 10 clear ocna/ocnb on compare match (set output to low level). 11 set ocna/ocnb on compare match (set output to high level). table 30. compare output mode, fast pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 01 wgmn3:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear ocna/ocnb on compare match, set ocna/ocnb at top 11 set ocna/ocnb on compare match, clear ocna/ocnb at top table 31. compare output mode, phase correct and phase and frequency correct pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 01 wgmn3:0 = 8, 9 10 or 11: toggle ocna on compare match, ocnb disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear ocna/ocnb on compare match when up- counting. set ocna/ocnb on compare match when downcounting. 11 set ocna/ocnb on compare match when up- counting. clear ocna/ocnb on compare match when downcounting. 118 4378c?avr?09/08 at90pwm1 note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. see ?phase correct pwm mode? on page 111. for more details. ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of wave - form generation to be used, see table 32 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?16-bit timer/counter1 with pwm? on page 96. ). note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 15.10.2 timer/counter1 control register b ? tccr1b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the input capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select table 32. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 40100ctc ocrnaimmediatemax 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icrn bottom bottom 91001 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn top top 15 1 1 1 1 fast pwm ocrna top top bit 7654 3210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 119 4378c?avr?09/08 at90pwm1 this bit selects which edge on the input capture pi n (icpn) that is used to trigger a capture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will also set the input capture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequently the input cap - ture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future devices, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 15-10 and figure 15-11 . if external pin modes are used for the timer/coun tern, transitions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 15.10.3 timer/counter1 control register c ? tccr1c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b the focna/focnb bits are only active when the wgmn3:0 bits specifies a non-pwm mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccrna is written when operating in a pwm mode. when writing a logical one to the focna/focnb bit, an immediate compare match is forced on the waveform generation unit. the ocna/ocnb output is changed according to its comnx1:0 bits setting. note that the table 33. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654 3210 foc1a foc1b ? ? ? ? ? ? tccr1c read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 120 4378c?avr?09/08 at90pwm1 focna/focnb bits are implemented as strobes. therefore it is the value present in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb bits are always read as zero. 15.10.4 timer/counter1 ? tcnt1h and tcnt1l the two timer/counter i/o locations (tcntnh and tcntnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 98. modifying the counter (tcntn) while the counter is running introduces a risk of missing a com - pare match between tcntn and one of the ocrnx registers. writing to the tcntn register blocks (removes) the compare match on the following timer clock for all compare units. 15.10.5 output compare register 1 a ? ocr1ah and ocr1al 15.10.6 output compare register 1 b ? ocr1bh and ocr1bl the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcntn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 98. bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 121 4378c?avr?09/08 at90pwm1 15.10.7 input capture register 1 ? icr1h and icr1l the input capture is updated with the counter (tcntn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 98. 15.10.8 timer/counter1 interrupt mask register ? timsk1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90pwm1, and will always read as zero. ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( see ?reset and interrupt vectors placement in at90pwm1(1)? on page 54 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the at90pwm1, and will always read as zero. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?reset and interrupt vectors placement in at90pwm1(1)? on page 54 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?reset and interrupt vectors placement in at90pwm1(1)? on page 54 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector ( see ?reset and interrupt vectors placement in at90pwm1(1)? on page 54 ) is executed when the tov1 flag, located in tifr1, is set. bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 122 4378c?avr?09/08 at90pwm1 15.10.9 timer/counter1 interrupt flag register ? tifr1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90pwm1, and will always read as zero. ? bit 5 ? icf1: timer/counter1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgmn3:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the at90pwm1, and will always read as zero. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is exe - cuted. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is exe - cuted. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wgm n3:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 32 on page 118 for the tov1 flag behavior when using another wgmn3:0 bit setting. tov1 is automatically cleared when the timer/counter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 ? ? icf1 ? ? ocf1b ocf1a tov1 tifr1 read/write r r r/w r r r/w r/w r/w initial value00000000 123 4378c?avr?09/08 at90pwm1 16. power stage controller ? (psc0, psc2) the power stage controller is a high performance waveform controller. 16.1 features ? pwm waveform generation function (2 complementary programmable outputs) ? dead time control ? standard mode up to 12 bit resolution ? frequency resolution enhancement mode (12 + 4 bits) ? frequency up to 64 mhz ? conditional waveform on external events (zero crossing, current sensing ...) ? all on chip psc synchronization ? adc synchronization ? overload protection function ? abnormality protection function, emergency input to force all outputs to high impedance or in inactive state (fuse configurable) ? center aligned and edge aligned modes synchronization ? fast emergency stop by hardware 16.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the psc number, in this case 0, 1 or 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., psoc1 for accessing psc 0 synchro and output configuration register and so on. ? a lower case ?x? replaces the psc part , in this case a or b. however, when using the register or bit defines in a program, the precise form must be used, i.e., pfrcna for accessing psc n fault/retrigger n a control register and so on. the purpose of a power stage controller (psc) is to control power modules on a board. it has two outputs on psc0 and psc1 and four outputs on psc2. these outputs can be used in various ways: ? ?two ouputs? to drive a half bridge (lighting, dc motor ...) ? ?one output? to drive single power transistor (dc/dc converter, pfc, dc motor ...) ? ?four outputs? in the case of psc2 to drive a full bridge (lighting, dc motor ...) each psc has two inputs the purpose of which is to provide means to act directly on the gener - ated waveforms: ? current sensing regulation ? zero crossing retriggering ? demagnetization retriggering ? fault input the psc can be chained and synchronized to provide a configuration to drive three half bridges. thanks to this feature it is possible to generate a three phase waveforms for applications such as asynchronous or bldc motor drive. 124 4378c?avr?09/08 at90pwm1 16.3 psc description figure 16-1. power stage controller 0 note: n = 0, 1 the principle of the psc is based on the use of a counter (psc counter). this counter is able to count up and count down from and to values stored in registers according to the selected run - ning mode. the psc is seen as two symetrical entities. one part named part a which generates the output pscoutn0 and the second one named part b which generates the pscoutn1 output. each part a or b has its own psc input module to manage selected input. databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ( from analog comparator n ouput ) ocrnsa = pcnfn pfrcnb pom2(psc2 only) picrn waveform generator a pscoutn0 pscinn part b part a piselnb piselna pscn input b pscn input a 125 4378c?avr?09/08 at90pwm1 16.3.1 psc2 distinctive feature figure 16-2. psc2 block diagram note: n = 2 psc2 has two supplementary outputs pscout22 and pscout23. thanks to a first selector pscout22 can duplicate pscout20 or pscout21. thanks to a second selector pscout23 can duplicate pscout20 or pscout21. the output matrix is a kind of 2*2 look up table which gives the possibility to program the output values according to a psc sequence ( see ?output matrix? on page 151. ) databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ( from analog comparator n ouput ) ocrnsa = pcnfn pfrcnb pom2(psc2 only) picrn waveform generator a pscoutn0 pscinn part a part b pscoutn2 pscoutn3 piselnb piselna pscn input b pscn input a pos23 pos22 output matrix 126 4378c?avr?09/08 at90pwm1 16.3.2 output polarity the polarity ?active high? or ?active low? of the psc outputs is programmable. all the timing dia - grams in the following examples are given in the ?active high? polarity. 16.4 signal description figure 16-3. psc external block view note: 1. available only for psc2 2. n = 0, 1 or 2 ocrnrb[11:0] ocrnra[11:0] ocrnsa[11:0] ocrnrb[15:12] ocrnsb[11:0] picrn[11:0] irq pscn synin pscinn analog comparator n output pscoutn0 pscoutn2 synout clk 4 12 12 12 12 clk pscoutn1 pscoutn3 12 pscnasy stopout stopin i/o pll (1) (1) (flank width modulation) 127 4378c?avr?09/08 at90pwm1 16.4.1 input description table 34. internal inputs note: 1. see figure 16-38 on page 152 table 35. block inputs 16.4.2 output description table 36. block outputs name description type width ocrnrb[1 1:0] compare value which reset signal on part b (pscoutn1) register 12 bits ocrnsb[1 1:0] compare value which set signal on part b (pscoutn1) register 12 bits ocrnra[1 1:0] compare value which reset signal on part a (pscoutn0) register 12 bits ocrnsa[1 1:0] compare value which set signal on part a (pscoutn0) register 12 bits ocrnrb[1 5:12] frequency resolution enhancement value (flank width modulation) register 4 bits clk i/o clock input from i/o clock signal clk pll clock input from pll signal synin synchronization in (from adjacent psc) (1) signal stopin stop input (for synchronized mode) signal name description type width pscinn input 0 used for retrigger or fault functions signal from a c input 1 used for retrigger or fault functions signal name description type width pscoutn0 psc n output 0 (from part a of psc) signal pscoutn1 psc n output 1 (from part b of psc) signal pscoutn2 (psc2 only) psc n output 2 (from part a or part b of psc) signal pscoutn3( psc2 only) psc n output 3 (from part a or part b of psc) signal 128 4378c?avr?09/08 at90pwm1 table 37. internal outputs note: 1. see figure 16-38 on page 152 2. see ?analog synchronization? on page 152. 16.5 functional description 16.5.1 waveform cycles the waveform generated by psc can be described as a sequence of two waveforms. the first waveform is relative to pscoutn0 output and part a of psc. the part of this waveform is sub-cycle a in the following figure. the second waveform is relative to pscoutn1 output and part b of psc. the part of this wave - form is sub-cycle b in the following figure. the complete waveform is ended with the end of sub-cycle b. it means at the end of waveform b. figure 16-4. cycle presentation in 1, 2 & 4 ramp mode name description type width synout synchronization output (1) signal picrn [11:0] psc n input capture register counter value at retriggering event register 12 bits irqpscn psc interrupt request : three souces, overflow, fault, and input capture signal pscnasy adc synchronization (+ amplifier syncho. ) (2) signal stopout stop output (for synchronized mode) 4 ramp mode 2 ramp mode 1 ramp mode sub-cycle a sub-cycle b psc cycle update ramp a0 ramp a1 ramp b0 ramp b1 ramp a ramp b 129 4378c?avr?09/08 at90pwm1 figure 16-5. cycle presentation in centered mode ramps illustrate the output of the psc counter included in the waveform generators. centered mode is like a one ramp mode which count down up and down. notice that the update of a new set of values is done regardless of ramp mode at the top of the last ramp. 16.5.2 running mode description waveforms and length of output signals are determined by time parameters (dt0, ot0, dt1, ot1) and by the running mode. four modes are possible : ? four ramp mode ? two ramp mode ? one ramp mode ? center aligned mode 16.5.2.1 four ramp mode in four ramp mode, each time in a cycle has its own definition figure 16-6. pscn0 & pscn1 basic waveforms in four ramp mode the input clock of psc is given by clkpsc. psc cycle update centered mode on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 130 4378c?avr?09/08 at90pwm1 pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with : on-time 0 = ocrnrah/l * 1/fclkpsc on-time 1 = ocrnrbh/l * 1/fclkpsc dead-time 0 = (ocrnsah/l + 2) * 1/fclkpsc dead-time 1 = (ocrnsbh/l + 2) * 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 2 * 1/fclkpsc 16.5.2.2 two ramp mode in two ramp mode, the whole cycle is divided in two moments one moment for pscn0 description with ot0 which gives the time of the whole moment one moment for pscn1 description with ot1 which gives the time of the whole moment figure 16-7. pscn0 & pscn1 basic waveforms in two ramp mode pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with : on-time 0 = (ocrnrah/l - ocrnsah/l) * 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) * 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) * 1/fclkpsc dead-time 1 = (ocrnsbh/l + 1) * 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 1/fclkpsc 16.5.2.3 one ramp mode in one ramp mode, pscoutn0 and pscoutn1 outputs can overlap each other. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 131 4378c?avr?09/08 at90pwm1 figure 16-8. pscn0 & pscn1 basic waveforms in one ramp mode on-time 0 = (ocrnrah/l - ocrnsah/l) * 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) * 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) * 1/fclkpsc dead-time 1 = (ocrnsbh/l - ocrnrah/l) * 1/fclkpsc note: minimal value for dead-time 0 = 1/fclkpsc 16.5.2.4 center aligned mode in center aligned mode, the center of pscn00 and pscn01 signals are centered. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 0 132 4378c?avr?09/08 at90pwm1 figure 16-9. pscn0 & pscn1 basic waveforms in center aligned mode on-time 0 = 2 * ocrnsah/l * 1/fclkpsc on-time 1 = 2 * (ocrnrbh/l - ocrnsbh/l + 1) * 1/fclkpsc dead-time = (ocrnsbh/l - ocrnsah/l) * 1/fclkpsc psc cycle = 2 * (ocrnrbh/l + 1) * 1/fclkpsc note: minimal value for psc cycle = 2 * 1/fclkpsc ocrnrah/l is not used to control psc output waveform timing. nevertheless, it can be useful to adjust adc synchronization ( see ?analog synchronization? on page 152. ). figure 16-10. run and stop mechanism in centered mode note: see ?psc 0 control register ? pctl0? on page 158. (or pctl2) 133 4378c?avr?09/08 at90pwm1 16.5.3 fifty percent waveform configuration when pscoutn0 and pscoutn1 have the same characteristics, it?s possible to configure the psc in a fifty percent mode. when the psc is in this configuration, it duplicates the ocrnsbh/l and ocrnrbh/l registers in ocrnsah/ l and ocrnrah/l registers. so it is not necessary to program ocrnsah/l and ocrnrah/l registers. 16.6 update of values to avoid unasynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the psc. the new set of values is calculated by sofware and the update is initiated by software. figure 16-11. update at the end of complete psc cycle. the software can stop the cycle before the end to update the values and restart a new psc cycle. 16.6.1 value update synchronization new timing values or psc output configuration can be written during the psc cycle. thanks to lock and autolock configuration bits, the new whole set of values can be taken into account after the end of the psc cycle. when autolock configuration is selected, the update of the psc internal registers will be done at the end of the psc cycle if the output compare register rb has been the last written. the autolock configuration bit is taken into account at the end of the first psc cycle. when lock configuration bit is set, there is no update. the update of the psc internal registers will be done at the end of the psc cycle if the lock bit is released to zero. the registers which update is synchronized thanks to lock and autolock are psocn, pom2, ocrnsah/l, ocrnrah/l, ocrnsbh/l and ocrnrbh/l. see these register?s description starting on page 156 . when set, autolock configuration bit prevails over lock configuration bit. see ?psc 0 configuration register ? pcnf0? on page 157. 16.7 enhanced resolution lamp ballast applications need an enhanced resolution down to 50hz. the method to improve the normal resolution is based on flank widt h modulation (also called fractional divider). cycles are grouped into frames of 16 cycles. cycles are modulated by a sequence given by the software psc regulation loop calculation writting in psc registers cycle with set i cycle with set i cycle with set i cycle with set i cycle with set j end of cycle request for an update 134 4378c?avr?09/08 at90pwm1 fractional divider number. the resulting output frequency is the average of the frequencies in the frame. the fractional divider (d) is given by ocrnrb[15:12]. the psc output period is directly equal to the pscoutn0 on time + dead time (ot0+dt0) and pscoutn1 on time + deadtime (ot1+dt1) values. these values are 12 bits numbers. the frequency adjustment can only be done in steps like the dedicated counters. the step width is defined as the frequency difference between two neighboring psc frequencies: with k is the number of clk psc period in a psc cycle and is given by the following formula: with f op is the output operating frequency. exemple, in normal mode, with maximum operating frequency 160 khz and f pll = 64 mhz, k equals 400. the resulting resolution is delta f equals 64mhz / 400 / 401 = 400 hz. in enhanced mode, the output frequency is the average of the frame formed by the 16 consecu - tive cycles. f b1 and f b2 are two neightboring base frequencies. then the frequency resolution is divided by 16. in the example above, the resolution equals 25 hz. ff 1 f 2 ? f pll k ---------- f pll k 1 + ----------- - ? f psc 1 kk 1 + () ------------------- - == = n f psc f op ---------- = f average 16 d ? 16 --------------- f b 1 d 16 ------ f b 2 + = f average 16 d ? 16 --------------- f pll n ---------- d 16 ------ f pll n 1 + ------------ + = 135 4378c?avr?09/08 at90pwm1 16.7.1 frequency distribution the frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame. these two frequencies are f b1 and f b2 where f b1 is the nearest base frequency above the wanted frequency and f b2 is the nearest base frequency below the wanted frequency. the number of f b1 in the frame is (d-16) and the number of f b2 is d. the f b1 and f b2 frequencies are evenly distrib - uted in the frame according to a predefined pattern. this pattern can be as given in the following table or by any other implementation which give an equivallent evenly distribution. table 38. distribution of f b2 in the modulated frame while ?x? in the table, f b2 prime to f b1 in cycle corresponding cycle. so for each row, a number of fb2 take place of fb1. figure 16-12. resulting frequency versus d. distribution of fb2 in the modulated frame pwm - cycle fraction al divider (d) 0123456789101112131415 0 1x 2x x 3x x x 4x x x x 5xxx x x 6xxx xxx 7xxxxxxx 8xxxxxxxx 9xxxxxxxxx 10 xxx x x xxx x x 11 xxx xxx xxx x x 12 xxx xxx xxx xxx 13 xxxxxxx xxx xxx 14 xxxxxxx xxxxxxx 15 xxxxxxxxxxxxxxx f b1 f b2 d: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f op 136 4378c?avr?09/08 at90pwm1 16.7.2 modes of operation 16.7.2.1 normal mode the simplest mode of operation is the normal mode. see figure 16-6 . the active time of pscoutn0 is given by the ot0 value. the active time of pscoutn1 is given by the ot1 value. both of them are 12 bit values. thanks to dt0 & dt1 to ajust the dead time between pscoutn0 and pscoutn1 active signals. the waveform frequency is defined by the following equation: 16.7.2.2 enhanced mode the enhanced mode uses the previously des cribed method to generate a high resolution frequency. figure 16-13. enhanced mode, timing diagram the supplementary step in counting to generate f b2 is added on the pscn0 signal while needed in the frame according to the fractional divider. see table 38, ?distribution of fb2 in the modu - lated frame,? on page 135 . the waveform frequency is defined by the following equations: d is the fractionel divider factor. f pscn 1 pscncycle ----------------------------- - = f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ () ---------------------------------------------------------------------- 1 === pscoutn0 t1 period pscoutn1 ot0 ot1 dt1 dt0 t2 ot0+1 ot1 dt1 dt0 dt0 f 1 pscn 1 t 1 ----- - f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ () ---------------------------------------------------------------------- == f 2 pscn 1 t 2 ----- - f clk_pscn ot 0 ot 1 dt 0 dt 11 ++++ () -------------------------------------------------------------------------------- == f average d 16 ------ f 1 pscn 16 d ? 16 --------------- f 2 pscn + = 137 4378c?avr?09/08 at90pwm1 16.8 psc inputs each part a or b of psc has its own system to take into account one psc input. according to psc n input a/b control register (see description 16.25.13 page 161 ), pscnin0/1 input can act has a retrigger or fault input. this system a or b is also configured by this psc n input a/b control register (pfrcna/b). figure 16-14. psc input module 16.8.1 psc retrigger behaviour versus psc running modes in centered mode, retrigger inputs have no effect. in two ramp or four ramp mode, retrigger inputs a or b cause the end of the corresponding cycle a or b and the beginning of the following cycle b or a. in one ramp mode, retrigger inputs a or b reset the current psc counting to zero. 16.8.2 retrigger pscoutn0 on external event pscoutn0 ouput can be resetted before end of on-time 0 on the change on pscn input a. pscn input a can be configured to do not act or to act on level or edge modes. the polarity of pscn input a is configurable thanks to a sense control block. pscn input a can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. analog comparator n output pscinn digital filter piselna (piselnb) pfltena (pfltenb) paocna (paocnb) input processing (retriggering ...) psc core (counter, waveform generator, ...) output control 1 0 0 1 pscoutn0 (pscoutn1) (pscout22) (pscout23) clk psc clk psc clk psc pelevna / (pelevnb) prfmna3:0 (prfmnb3:0) pcaena (pcaenb) 2 4 138 4378c?avr?09/08 at90pwm1 figure 16-15. pscoutn0 retriggered by pscn input a (edge retriggering) note: this exemple is given in ?input mode 8? in ?2 or 4 ramp mode? see figure 16-31. for details. figure 16-16. pscoutn0 retriggered by pscn input a (level acting) note: this exemple is given in ?input mode 1? in ?2 or 4 ramp mode? see figure 16-20. for details. 16.8.3 retrigger pscoutn1 on external event pscoutn1 ouput can be resetted before end of on-time 1 on the change on pscn input b. the polarity of pscn input b is configurable thanks to a sense control block. pscn input b can be configured to do not act or to act on level or edge modes. pscn input b can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (falling edge) pscn input a (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (high level) pscn input a (low level) 139 4378c?avr?09/08 at90pwm1 figure 16-17. pscoutn1 retriggered by pscn input b (edge retriggering) note: this exemple is given in ?input mode 8? in ?2 or 4 ramp mode? see figure 16-31. for details. figure 16-18. pscoutn1 retriggered by pscn input b (level acting) note: this exemple is given in ?input mode 1? in ?2 or 4 ramp mode? see figure 16-20. for details. 16.8.3.1 burst generation note: on level mode, it?s possible to use psc to generate burst by using input mode 3 or mode 4 ( see figure 16-24. and figure 16-25. for details.) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (falling edge) pscn input b (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (high level) pscn input b (low level) 140 4378c?avr?09/08 at90pwm1 figure 16-19. burst generation 16.8.4 psc input configuration the psc input configuration is done by programming bits in configuration registers. 16.8.4.1 filter enable if the ?filter enable? bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. the disable of this function is mainly needed for prescaled psc clock sources, where the noise cancellation gives too high latency. important: if the digital filter is active, the level sensitivity is true also with a disturbed psc clock to deactivate the outputs (emergency protection of external component). likewise when used as fault input, pscn input a or input b have to go through psc to act on pscoutn0/1/2/3 output. this way needs that clk psc is running. so thanks to psc asynchronous output control bit (paocna/b), pscnin0/1 input can desactivate directly the psc output. notice that in this case, input is still taken into account as usually by input module system as soon as clk psc is running. psc input filterring 16.8.4.2 signal polarity one can select the active edge (edge modes) or the active level (level modes) see pelevnx bit description in section ?psc n input a control register ? pfrcna?, page 161 16.25.13 . off pscoutn0 pscoutn1 pscn input a (high level) pscn input a (low level) burst digital filter 4 x clk psc input module x ouput stage pscoutnx pin pscn input a or b clk psc psc 141 4378c?avr?09/08 at90pwm1 if pelevnx bit set, the significant edge of pscn input a or b is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - in 2- or 4-ramp mode, pscn input a is taken into account only during dead-time0 and on- time0 period (respectively dead-time1 and on-time1 for pscn input b). - in 1-ramp-mode psc input a or psc input b act on the whole ramp. 16.8.4.3 input mode operation thanks to 4 configuration bits (prfm3:0), it?s possible to define the mode of the psc input. all notice: all following examples are given with rising edge or high level active inputs. table 39. psc input mode operation prfm3:0 description 0 0000b pscn input has no action on psc output 1 0001b 16.9 see ?psc input mode 1: stop signal, jump to opposite dead-time and wait? on page 142. 2 0010b see ?psc input mode 2: stop signal, execute opposite dead-time and wait? on page 143. 3 0011b see ?psc input mode 3: stop signal, execute opposite while fault active? on page 144. 4 0100b see ?psc input mode 4: deactivate outputs without changing timing.? on page 144. 5 0101b see ?psc input mode 5: stop signal and insert dead-time? on page 145. 6 0110b see ?psc input mode 6: stop signal, jump to opposite dead-time and wait.? on page 146. 70111b see ?psc input mode 7: halt psc and wait for software action? on page 146. 8 1000b see ?psc input mode 8: edge retrigger psc? on page 147. 9 1001b see ?psc input mode 9: fixed frequency edge retrigger psc? on page 148. 10 1010b reserved : do not use 11 1011b 12 1100b 13 1101b 14 1110b see ?psc input mode 14: fixed frequency edge retrigger psc and dis - activate output? on page 149. 15 1111b reserved : do not use 142 4378c?avr?09/08 at90pwm1 16.9 psc input mode 1: stop signal, ju mp to opposite dead-time and wait figure 16-20. pscn behaviour versus pscn input a in fault mode 1 psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, waits for psc input a inactive state and then jumps and executes dt1 plus ot1. figure 16-21. pscn behaviour versus pscn input b in fault mode 1 psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscoutn1, waits for psc input b inactive state and then jumps and executes dt0 plus ot0. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 143 4378c?avr?09/08 at90pwm1 16.10 psc input mode 2: stop signal, execute opposite dead-time and wait figure 16-22. pscn behaviour versus pscn input a in fault mode 2 psc input a is take into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscn input a event occurs, psc releases pscoutn0, jumps and executes dt1 plus ot1 and then waits for psc input a inactive state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com - pletely executed. figure 16-23. pscn behaviour versus pscn input b in fault mode 2 psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscoutn1, jumps and executes dt0 plus ot0 and then waits for psc input b inactive state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com - pletely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 144 4378c?avr?09/08 at90pwm1 16.11 psc input mode 3: stop signal, execute opposite while fault active figure 16-24. pscn behaviour versus pscn input a in mode 3 psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, jumps and executes dt1 plus ot1 plus dt0 while psc input a is in active state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com - pletely executed. figure 16-25. pscn behaviour versus pscn input b in mode 3 psc input b is taken into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscnout1, jumps and executes dt0 plus ot0 plus dt1 while psc input b is in active state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com - pletely executed. 16.12 psc input mode 4: deactivate outputs without changing timing. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 ot1 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 145 4378c?avr?09/08 at90pwm1 figure 16-26. psc behaviour versus pscn input a or input b in mode 4 figure 16-27. psc behaviour versus pscn input a or input b in fault mode 4 pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on- time1/dead-time1. 16.13 psc input mode 5: stop signal and insert dead-time figure 16-28. psc behaviour versus pscn input a in fault mode 5 used in fault mode 5, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 pscn input a or pscn input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 dt1 dt0 dt0 pscn input a or pscn input b dt0 dt1 146 4378c?avr?09/08 at90pwm1 16.14 psc input mode 6: stop signal, ju mp to opposite dead-time and wait. figure 16-29. psc behaviour versus pscn input a in fault mode 6 used in fault mode 6, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. 16.15 psc input mode 7: halt psc and wait for software action figure 16-30. psc behaviour versus pscn input a in fault mode 7 note: 1. software action is the setting of the prunn bit in pctln register. used in fault mode 7, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 software action (1) pscn input a or pscn input b 147 4378c?avr?09/08 at90pwm1 16.16 psc input mode 8: edge retrigger psc figure 16-31. psc behaviour versus pscn input a in mode 8 the output frequency is modulated by the occurence of significative edge of retriggering input. figure 16-32. psc behaviour versus pscn input b in mode 8 the output frequency is modulated by the occurence of significative edge of retriggering input. the retrigger event is taken into account only if it occurs during the corresponding on-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b pscn input b or 148 4378c?avr?09/08 at90pwm1 16.17 psc input mode 9: fixed frequency edge retrigger psc figure 16-33. psc behaviour versus pscn input a in mode 9 the output frequency is not modified by the occurence of significative edge of retriggering input. only the output is disactivated when significative edge on retriggering input occurs. note: in this mode the output of the psc becomes active during the next ramp even if the retrig - ger/fault input is actve. only the significative edge of retrigger/fault input is taken into account. figure 16-34. psc behaviour versus pscn input b in mode 9 the retrigger event is taken into account only if it occurs during the corresponding on-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b 149 4378c?avr?09/08 at90pwm1 16.18 psc input mode 14: fi xed frequency edge retrigger psc and disactivate output figure 16-35. psc behaviour versus pscn input a in mode 14 the output frequency is not modified by the occurence of significative edge of retriggering input. figure 16-36. psc behaviour versus pscn input b in mode 14 the output is disactivated while retriggering input is active. the output of the psc is set to an inactive state and the corresponding ramp is not aborted. the output stays in an inactive state while the retrigger/fault input is actve. the psc runs at con - stant frequency. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input b 150 4378c?avr?09/08 at90pwm1 16.18.1 available input mode according to running mode some input modes are not consistent with some running modes. so the table below gives the input modes which are valid according to running modes.. 16.18.2 event capture the psc can capture the value of time (psc counter) when a retrigger event or fault event occurs on psc inputs. this value can be read by sofware in picrnh/l register. 16.18.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the picrn register before the next event occurs, the picrn will be overwritten with a new value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the picrn register should be read as early in the inter - rupt handler routine as possible. even though th e input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. table 40. available input modes according to running modes input mode number : 1 ramp mode 2 ramp mode 4 ramp mode centered mode 1 valid valid valid do not use 2 do not use valid valid do not use 3 do not use valid valid do not use 4 valid valid valid valid 5 do not use valid valid do not use 6 do not use valid valid do not use 7 valid valid valid valid 8 valid valid valid do not use 9 valid valid valid do not use 10 do not use 11 12 13 14 valid valid valid do not use 15 do not use 151 4378c?avr?09/08 at90pwm1 16.19 psc2 outputs 16.19.1 output matrix psc2 has an output matrix which allow in 4 ramp mode to program a value of pscout20 and pscout21 binary value for each ramp. pscout2m takes the value given in table 41. during all corresponding ramp. thanks to the output matrix it is possible to generate all kind of pscout20/pscout21 combination. when output matrix is used, the psc n output polarity popn has no action on the outputs. 16.19.2 pscout22 & pscout23 selectors psc 2 has two supplementary outputs pscout22 and pscout23. according to pos22 and pos23 bits in psoc2 register, pscout22 and pscout23 duplicate pscout20 and pscou21. if pos22 bit in psoc2 register is clear, pscout22 duplicates pscout20. if pos22 bit in psoc2 register is set, pscout22 duplicates pscout21. if pos23 bit in psoc2 register is clear, pscout23 duplicates pscout21. if pos23 bit in psoc2 register is set, pscout23 duplicates pscout20. figure 16-37. pscout22 and pscout23 outptuts table 41. output matrix versus ramp number ramp 0 ramp 1 ramp 2 ramp 3 pscout20 pomv2a0 pomv2a1 pomv2a2 pomv2a3 pscout21 pomv2b0 pomv2b1 pomv2b2 pomv2b3 pscout20 pscout21 waveform generator a waveform generator b pscout22 pscout23 pos22 pos23 0 1 1 0 output matrix 152 4378c?avr?09/08 at90pwm1 16.20 analog sy nchronization psc generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. this signal can be selected between all falling or rising edge of pscn0 or pscn1 outputs. in center aligned mode, ocrnrah/l is not used, so it can be used to specified the synchroniza - tion of the adc. it this case, it?s minimum value is 1. 16.21 interrupt handling as each psc can be dedicated for one function, each psc has its own interrupt system (vector ...) list of interrupt sources: ? counter reload (end of on time 1) ? psc input event (active edge or at the beginning of level configured event) ? psc mutual synchronization error 16.22 psc synchronization 2 or 3 psc can be synchronized together. in this case, two waveform alignments are possible: ? the waveforms are center aligned in the center aligned mode if master and slaves are all with the same psc period (which is the natural use). ? the waveforms are edge aligned in the 1, 2 or 4 ramp mode figure 16-38. psc run synchronization 153 4378c?avr?09/08 at90pwm1 if the pscm has its parunn bit set, then it can start at the same time than pscn-1. prunn and parunn bits are located in pctln register. see ?psc 0 control register ? pctl0? on page 158. see ?psc 1 control register ? pctl1? on page 160. see ?psc 2 control register ? pctl2? on page 160. note : do not set the parunn bits on the three psc at the same time. thanks to this feature, we can for example configure two psc in slave mode (parunn = 1 / prunn = 0) and one psc in master mode (parunm = 0 / prunm = 0). this psc master can start all psc at the same moment ( prunm = 1). 16.22.1 fault events in autorun mode to complete this master/slave mechanism, fault event (input mode 7) is propagated from pscn- 1 to pscn and from pscn to pscn-1. a psc which propagate a run signal to the following psc stops this psc when the run signal is deactivate. according to the architecture of the psc synchronization which build a ?daisy-chain on the psc run signal? beetwen the three psc, only the fault event (mode 7) which is able to ?stop? the psc through the prun bits is transmited along this daisy-chain. a psc which receive its run signal from the previous psc transmits its fault signal (if enabled) to this previous psc. so a slave psc propagates its fault events when they are configured and enabled. 16.23 psc clock sources psc must be able to generate high frequency with enhanced resolution. each psc has two clock inputs: ? clk pll from the pll ? clk i/o figure 16-39. clock selection pclkseln bit in psc n configuration register (pcnfn) is used to select the clock source. ppren1/0 bits in psc n control register (pctln) are used to select the divide factor of the clock. 154 4378c?avr?09/08 at90pwm1 16.24 interrupts this section describes the specifics of the interrupt handling as performed in at90pwm1. 16.24.1 list of interrupt vector each psc provides 2 interrupt vectors ? pscn ec (end of cycle ): when enabled and when a match with ocrnrb occurs ? pscn capt (capture event) : when enabled and one of the two following events occurs : retrigger, capture of the psc counter or synchro error. 16.26.216.26.2see pscn interrupt mask register page 164 and pscn interrupt flag register page 164 . 16.24.2 psc interrupt vectors in at90pwm1 16.25 psc register definition registers are explained for psc0. they are identical for psc1. for psc2 only different registers are described. table 42. output clock versus selection and prescaler pclkseln ppren1 ppren0 clkpscn output at90pwm1 000clk i/o 0 0 1 clk i/o / 4 0 1 0 clk i/o / 32 0 1 1 clk i/o / 256 100clk pll 1 0 1 clk pll / 4 1 1 0 clk pll / 32 1 1 1 clk pll / 256 table 43. psc interrupt vectors vector no. program address source interrupt definition -- -- 2 0x0001 psc2 capt psc2 capture event or synchronization error 3 0x0002 psc2 ec psc2 end cycle 6 0x0005 psc0 capt psc0 capture event or synchronization error 7 0x0006 psc0 ec psc0 end cycle -- -- 155 4378c?avr?09/08 at90pwm1 16.25.1 psc 0 synchro and output configuration ? psoc0 16.25.2 psc 2 synchro and output configuration ? psoc2 ? bit 7 ? pos23 : pscout23 selection (psc2 only) when this bit is clear, pscout23 outputs the waveform generated by waveform generator b. when this bit is set, pscout23 outputs the waveform generated by waveform generator a. ? bit 6 ? pos22 : pscout22 selection (psc2 only) when this bit is clear, pscout22 outputs the waveform generated by waveform generator a. when this bit is set, pscout22 outputs the waveform generated by waveform generator b. ? bit 5:4 ? psyncn1:0: synchr onization out for adc selection select the polarity and signal source for generating a signal which will be sent to the adc for synchronization. ? bit 3 ? poen2d : pscout23 output enable (psc2 only) when this bit is clear, second i/o pin affected to pscout23 acts as a standard port. when this bit is set, second i/o pin affected to pscout23 is connected to the psc waveform generator b output and is set and clear according to the psc operation. bit 7 6543210 - - psync01 psync00 - poen0b - poen0a psoc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6543210 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a psoc2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 table 44. synchronization source description in one/two/four ramp modes psyncn1 psyncn0 description 0 0 send signal on leading edge of pscoutn0 (match with ocrnsa) 01 send signal on trailing edge of pscoutn0 (match with ocrnra or fault/retrigger on part a) 1 0 send signal on leading edge of pscoutn1 (match with ocrnsb) 11 send signal on trailing edge of pscoutn1 (match with ocrnrb or fault/retrigger on part b) table 45. synchronization source description in centered mode psyncn1 psyncn0 description 00 send signal on match with ocrnra (during counting down of psc). the min value of ocrnra must be 1. 01 send signal on match with ocrnra (during counting up of psc). the min value of ocrnra must be 1. 1 0 no synchronization signal 1 1 no synchronization signal 156 4378c?avr?09/08 at90pwm1 ? bit 2 ? poennb: psc n out part b output enable when this bit is clear, i/o pin affected to pscoutn1 acts as a standard port. when this bit is set, i/o pin affected to pscoutn1 is connected to the psc waveform generator b output and is set and clear according to the psc operation. ? bit 1 ? poen2c : pscout22 output enable (psc2 only) when this bit is clear, second i/o pin affected to pscout22 acts as a standard port. when this bit is set, second i/o pin affected to pscout22 is connected to the psc waveform generator a output and is set and clear according to the psc operation. ? bit 0 ? poenna: psc n out part a output enable when this bit is clear, i/o pin affected to pscoutn0 acts as a standard port. when this bit is set, i/o pin affected to pscoutn0 is connected to the psc waveform generator a output and is set and clear according to the psc operation. 16.25.3 output compare sa register ? ocrnsah and ocrnsal 16.25.4 output compare ra regi ster ? ocrnrah and ocrnral bit 76543210 ? ? ? ? ocrnsa[11:8] ocrnsah ocrnsa[7:0] ocrnsal read/write wwwwwwww initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ? ? ocrnra[11:8] ocrnrah ocrnra[7:0] ocrnral read/write wwwwwwww initial value 0 0 0 0 0 0 0 0 157 4378c?avr?09/08 at90pwm1 16.25.5 output compare sb register ? ocrnsbh and ocrnsbl 16.25.6 output compare rb regi ster ? ocrnrbh and ocrnrbl note : n = 0 to 2 according to psc number. the output compare registers ra, rb, sa and sb contain a 12-bit value that is continuously compared with the psc counter value. a match can be used to generate an output compare interrupt, or to generate a waveform output on the associated pin. the output compare registers rb contains also a 4-bit value that is used for the flank width modulation. the output compare registers are 16bit and 12-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writ es to these registers, the access is per - formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. 16.25.7 psc 0 configuration register ? pcnf0 16.25.8 psc 1 configuration register ? pcnf1 16.25.9 psc 2 configuration register ? pcnf2 the psc n configuration register is used to configure the running mode of the psc. ? bit 7 - pfiftyn: psc n fifty writing this bit to one, set the psc in a fifty percent mode where only ocrnrbh/l and ocrnsbh/l are used. they are duplicated in ocrnrah/l and ocrnsah/l during the update of ocrnrbh/l. this feature is useful to perform fifty percent waveforms. bit 76543210 ? ? ? ? ocrnsb[11:8] ocrnsbh ocrnsb[7:0] ocrnsbl read/write wwwwwwww initial value 0 0 0 0 0 0 0 0 bit 76543210 ocrnrb[15:12] ocrnrb[11:8] ocrnrbh ocrnrb[7:0] ocrnrbl read/write wwwwwwww initial value 0 0 0 0 0 0 0 0 bit 7 6543210 pfifty0 palock0 plock0 pmode01 pmode00 pop0 pclksel0 - pcnf0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6543210 pfifty1 palock1 plock1 pmode11 pmode10 pop1 pclksel1 - pcnf1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6543210 pfifty2 palock2 plock2 pmode21 pmode20 pop2 pclksel2 pome2 pcnf2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 158 4378c?avr?09/08 at90pwm1 ? bit 6 - palockn: psc n autolock when this bit is set, the output compare regi sters ra, sa, sb, the output matrix pom2 and the psc output configuration psocn can be written without disturbing the psc cycles. the update of the psc internal registers will be done at the end of the psc cycle if the output com - pare register rb has been the last written. when set, this bit prevails over lock (bit 5) ? bit 5 ? plockn: psc n lock when this bit is set, the output compare regist ers ra, rb, sa, sb, the output matrix pom2 and the psc output configuration psocn can be written without disturbing the psc cycles. the update of the psc internal registers will be done if the lock bit is released to zero. ? bit 4:3 ? pmoden1: 0: psc n mode select the mode of psc. ? bit 2 ? popn: psc n output polarity if this bit is cleared, the psc outputs are active low. if this bit is set, the psc outputs are active high. ? bit 1 ? pclkseln: psc n input clock select this bit is used to select between clkpf or clkps clocks. set this bit to select the fast clock input (clkpf). clear this bit to select the slow clock input (clkps). ? bit 0 ? pome2: psc 2 output matrix enable (psc2 only) set this bit to enable the output matrix feature on psc2 outputs. see ?psc2 outputs? on page 151 . when output matrix is used, the psc n output polarity popn has no action on the outputs. 16.25.10 psc 0 control register ? pctl0 table 46. psc n mode selection pmoden1 pmoden0 description 0 0 one ramp mode 0 1 two ramp mode 1 0 four ramp mode 1 1 center aligned mode bit 7 6543210 ppre01 ppre00 pbfm0 paoc0b paoc0a parun0 pccyc0 prun0 pctl0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 159 4378c?avr?09/08 at90pwm1 ? bit 7:6 ? ppre01:0 : psc 0 prescaler select this two bits select the psc input clock division factor. all generated waveform will be modified by this factor. ? bit 5 ? pbfm0 : balance flank width modulation when this bit is clear, flank width modulation operates on on-time 1 only. when this bit is set, flank width modulation operates on on-time 0 and on-time 1. ? bit 4 ? paoc0b : psc 0 asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscout01 output. see section ?psc input configuration?, page 140 . ? bit 3 ? paoc0a : psc 0 asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscout00 output. see section ?psc input configuration?, page 140 . ? bit 2 ? parun0 : psc 0 autorun when this bit is set, the psc 0 starts with psc2. that means that psc 0 starts : ? when prun2 bit in pctl2 is set, ? or when parun2 bit in pctl2 is set and prun1 bit in pctl1 register is set. thanks to this bit, 2 or 3 pscs can be synchronized (motor control for example) ? bit 1 ? pccyc0 : psc 0 complete cycle when this bit is set, the psc 0 completes the entire waveform cycle before halt operation requested by clearing prun0. this bit is not relevant in slave mode (parun0 = 1). ? bit 0 ? prun0 : psc 0 run writing this bit to one starts the psc 0. when set, this bit prevails over parun0 bit. table 47. psc 0 prescaler selection ppre01 ppre00 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 16 1 1 divide the psc clock by 64 160 4378c?avr?09/08 at90pwm1 16.25.11 psc 1 control register ? pctl1 ? bit 2 ? parun1 : psc 1 autorun when this bit is set, the psc 1 starts with psc0. that means that psc 1 starts : ? when prun0 bit in pctl0 register is set, ? or when parun0 bit in pctl0 is set and prun2 bit in pctl2 register is set. thanks to this bit, 2 or 3 pscs can be synchronized (motor control for example. 16.25.12 psc 2 control register ? pctl2 ? bit 7:6 ? ppre21:0 : psc 2 prescaler select this two bits select the psc input clock division factor.all generated waveform will be modified by this factor. ? bit 5 ? pbfm2 : balance flank width modulation when this bit is clear, flank width modulation operates on on-time 1 only. when this bit is set, flank width modulation operates on on-time 0 and on-time 1. ? bit 4 ? paoc2b : psc 2 asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscout21 and pscout23 outputs. see section ?psc clock sources?, page 153 . ? bit 3 ? paoc2a : psc 2 asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscout20 and pscout22 outputs. see section ?psc clock sources?, page 153 . ? bit 2 ? parun2 : psc 2 autorun when this bit is set, the psc 2 starts with psc1. that means that psc 2 starts : ? when prun1 bit in pctl1 register is set, ? or when parun1 bit in pctl1 is set and prun0 bit in pctl0 register is set. bit 2 parun1 read/write r/w initial value 0 bit 7 6543210 ppre21 ppre20 pbfm2 paoc2b paoc2a parun2 pccyc2 prun2 pctl2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 table 48. psc 2 prescaler selection ppre21 ppre20 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 16 1 1 divide the psc clock by 64 161 4378c?avr?09/08 at90pwm1 ? bit 1 ? pccyc2 : psc 2 complete cycle when this bit is set, the psc 2 completes the entire waveform cycle before halt operation requested by clearing prun2. this bit is not relevant in slave mode (parun2 = 1). ? bit 0 ? prun2 : psc 2 run writing this bit to one starts the psc 2. when set, this bit prevails over parun2 bit. 16.25.13 psc n input a control register ? pfrcna 16.25.14 psc n input b control register ? pfrcnb the input control registers are used to configure the 2 psc?s retrigger/fault block a & b. the 2 blocks are identical, so they are configured on the same way. ? bit 7 ? pcaenx : psc n capture enable input part x writing this bit to one enables the capture function when external event occurs on input selected as input for part x (see piselnx bit in the same register). ? bit 6 ? piselnx : psc n input select for part x clear this bit to select pscinn as input of fault/retrigger block x. set this bit to select comparator n output as input of fault/retrigger block x. ? bit 5 ?pelevnx : psc n edge level selector of input part x when this bit is clear, the falli ng edge or low level of selected input generates the significative event for retrigger or fault function . when this bit is set, the rising edge or high level of selected input generates the significative event for retrigger or fault function. ? bit 4 ? pfltenx : psc n filter enable on input part x setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the retrigger pin is filtered. the filter function requires four successive equal valued samples of the retrigger pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. bit 7 6543210 pcaena piselna pelevna pfltena prfmna3 prfmna2 prfmna1 prfmna0 pfrcna read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6543210 pcaenb piselnb pelevnb pfltenb prfmnb3 prfmnb2 prfmnb1 prfmnb0 pfrcnb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 162 4378c?avr?09/08 at90pwm1 ? bit 3:0 ? prfmnx3:0: psc n fault mode these four bits define the mode of operation of the fault or retrigger functions. (see psc functional specification for more explanations) table 49. level sensitivity and fault mode operation 16.25.15 psc 0 input capture register ? picr0h and picr0l 16.25.16 psc 2 input capture register ? picr2h and picr2l prfmnx3:0 description 0000b no action, psc input is ignored 0001b psc input mode 1: stop signal, jump to opposite dead-time and wait 0010b psc input mode 2: stop signal, execute opposite dead-time and wait 0011b psc input mode 3: stop signal, execute opposite while fault active 0100b psc input mode 4: deactivate outputs without changing timing. 0101b psc input mode 5: stop signal and insert dead-time 0110b psc input mode 6: stop signal, jump to opposite dead-time and wait. 0111b psc input mode 7: halt psc and wait for software action 1000b psc input mode 8: edge retrigger psc 1001b psc input mode 9: fixed frequency edge retrigger psc 1010b reserved (do not use) 1011b 1100b 1101b 1110b psc input mode 14: fixed frequency edge retrigger psc and disactivate output 1111b reserved (do not use) bit 76543210 pcst0 ? ? ? picr0[11:8] picr0h picr0[7:0] picr0l read/write rrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 pcst2 ? ? ? picr2[11:8] picr2h picr2[7:0] picr2l read/write rrrrrrrr initial value 0 0 0 0 0 0 0 0 163 4378c?avr?09/08 at90pwm1 ? bit 7 ? pcstn : psc capture software trig bit set this bit to trigger off a capture of the psc counter. when reading, if this bit is set it means that the capture operation was triggered by pcstn setting otherwise it means that the capture operation was triggered by a psc input. the input capture is updated with the psc counter value each time an event occurs on the enabled psc input pin (or optionally on the analog comparator output) if the capture function is enabled (bit pcaenx in pfrcnx register is set). the input capture register is 12-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit or 12-bit registers. 16.26 psc2 specific register 16.26.1 psc 2 output matrix ? pom2 ? bit 7 ? pomv2b3: output matrix output b ramp 3 this bit gives the state of the pscout21 (and/or pscout23) during ramp 3 ? bit 6 ? pomv2b2: output matrix output b ramp 2 this bit gives the state of the pscout21 (and/or pscout23) during ramp 2 ? bit 5 ? pomv2b1: output matrix output b ramp 1 this bit gives the state of the pscout21 (and/or pscout23) during ramp 1 ? bit 4 ? pomv2b0: output matrix output b ramp 0 this bit gives the state of the pscout21 (and/or pscout23) during ramp 0 ? bit 3 ? pomv2a3: output matrix output a ramp 3 this bit gives the state of the pscout20 (and/or pscout22) during ramp 3 ? bit 2 ? pomv2a2: output matrix output a ramp 2 this bit gives the state of the pscout20 (and/or pscout22) during ramp 2 ? bit 1 ? pomv2a1: output matrix output a ramp 1 this bit gives the state of the pscout20 (and/or pscout22) during ramp 1 ? bit 0 ? pomv2a0: output matrix output a ramp 0 this bit gives the state of the pscout20 (and/or pscout22) during ramp 0 bit 7 6543210 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 pom2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 164 4378c?avr?09/08 at90pwm1 16.26.2 psc0 interrupt mask register ? pim0 16.26.3 psc2 interrupt mask register ? pim2 ? bit 5 ? pseien : psc n synchro error interrupt enable when this bit is set, the psein bit (if set) generate an interrupt. ? bit 4 ? pevenb : psc n external event b interrupt enable when this bit is set, an external event which can generates a capture from retrigger/fault block b generates also an interrupt. ? bit 3 ? pevena : psc n external event a interrupt enable when this bit is set, an external event which can generates a capture from retrigger/fault block a generates also an interrupt. ? bit 0 ? peopen : psc n end of cycle interrupt enable when this bit is set, an interrupt is generated when psc reaches the end of the whole cycle. 16.26.4 psc0 interrupt flag register ? pifr0 16.26.5 psc2 interrupt flag register ? pifr2 ? bit 7 ? poacnb : psc n output b activity (not implemented on at90pwm1) this bit is set by hardware each time the output pscoutn1 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a psc output doesn?t change due to a freezen external input signal. ? bit 6 ? poacna : psc n output a activity (not implemented on at90pwm1) this bit is set by hardware each time the output pscoutn0 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. bit 7 6543210 - - pseie0 peve0b peve0a - - peope0 pim0 read/write r r r/w r/w r/w r r r/w initial value 0 0000000 bit 7 6543210 - - pseie2 peve2b peve2a - - peope2 pim2 read/write r r r/w r/w r/w r r r/w initial value 0 0000000 bit 7 6543210 poac0b poac0a psei0 pev0b pev0a prn01 prn00 peop2 pifr0 read/write r r r/w r/w r/w r r r/w initial value 0 0000000 bit 7 6543210 poac2b poac2a psei2 pev2b pev2a prn21 prn20 peop2 pifr2 read/write r r r/w r/w r/w r r r/w initial value 0 0000000 165 4378c?avr?09/08 at90pwm1 this feature is useful to detect that a psc output doesn?t change due to a freezen external input signal. ? bit 5 ? psein : psc n synchro error interrupt this bit is set by hardware when the update (or end of psc cycle) of the pscn configured in auto run (parunn = 1) does not occur at the same time than the pscn-1 which has generated the input run signal. (for psc0, pscn-1 is psc2). must be cleared by software by writing a one to its location. this feature is useful to detect that a psc doesn?t run at the same speed or with the same phase than the psc master. ? bit 4 ? pevnb : psc n external event b interrupt this bit is set by hardware when an external event which can generates a capture or a retrigger from retrigger/fault block b occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding interrupt is not enabled (pevenb bit = 0). ? bit 3 ? pevna : psc n external event a interrupt this bit is set by hardware when an external event which can generates a capture or a retrigger from retrigger/fault block a occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding interrupt is not enabled (pevena bit = 0). ? bit 2:1 ? prnn1:0 : psc n ramp number memorization of the ramp number when the last pevna or pevnb occured . ? bit 0 ? peopn: end of psc n interrupt this bit is set by hardware when psc n achieves its whole cycle. must be cleared by software by writing a one to its location. table 50. psc n ramp number description prnn1 prnn0 description 0 0 the last event which has generated an interrupt occured during ramp 1 0 1 the last event which has generated an interrupt occured during ramp 2 1 0 the last event which has generated an interrupt occured during ramp 3 1 1 the last event which has generated an interrupt occured during ramp 4 166 4378c?avr?09/08 at90pwm1 17. serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90pwm1 and peripheral devices or between several avr devices. the at90pwm1 spi includes the following features: 17.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode figure 17-1. spi block diagram (1) note: 1. refer to figure 3-1 on page 2 , and table 9 on page 65 for spi pin placement. the interconnection between master and slave cpus with spi is shown in figure 17-2 . the sys - tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates spi2x spi2x divider /2/4/8/16/32/64/128 clk io miso miso _a mosi mosi _a sck sck _a ss ss_a spips 167 4378c?avr?09/08 at90pwm1 the required clock pulses on the sck line to interchange data. data is always shifted from mas - ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after sh ifting one byte, the spi clock gener ator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 17-2. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direc - tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth - erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 51 . for more details on automatic port overrides, refer to ?alternate port functions? on page 63 . table 51. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input shift enable 168 4378c?avr?09/08 at90pwm1 note: 1. see ?alternate functions of port b? on page 65 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. miso input user defined sck user defined input ss user defined input table 51. spi pin overrides (1) pin direction, master spi direction, slave spi 169 4378c?avr?09/08 at90pwm1 note: 1. the example code assumes that the part specific header file is included. the following code examples show how to initialize the spi as a slave and how to perform a simple reception. table 2. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 172 4378c?avr?09/08 at90pwm1 ? when the spips bit is written to one,the spi signals are directed on pins miso,mosi, sck and ss. note that programming port are always located on alternate spi port. 17.2.4 spi control register ? spcr ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi mas - ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 17-3 and figure 17-4 for an example. the cpol functionality is sum - marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 17-3 and figure 17-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 bit 76543210 spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 52. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 53. cpha functionality cpha leading edge trailing edge 0 sample setup 1setupsample 173 4378c?avr?09/08 at90pwm1 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io frequency f clkio is shown in the following table: 17.2.5 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at90pwm1 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 54 ). this means that the minimum sck period will be two cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the at90pwm1 is also used for program memory and eeprom down - loading or uploading. see serial programming algorithm234 for serial programming and verification. table 54. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f clkio / 4 001 f clkio / 16 010 f clkio / 64 011 f clkio / 128 100 f clkio / 2 101 f clkio / 8 110 f clkio / 32 111 f clkio / 64 bit 76543210 spif wcol ? ? ? ? ? spi2x spsr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 174 4378c?avr?09/08 at90pwm1 17.2.6 spi data register ? spdr ? bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis - ter causes the shift register receive buffer to be read. 17.3 data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 17-3 and figure 17-4 . data bits are shifted out and latched in on opposite edges of the sck sig - nal, ensuring sufficient time for data signals to stabilize. this is clearly seen by summarizing table 52 and table 53 , as done below: figure 17-3. spi transfer format with cpha = 0 bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxxundefined table 55. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) 175 4378c?avr?09/08 at90pwm1 figure 17-4. spi transfer format with cpha = 1 sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 176 4378c?avr?09/08 at90pwm1 18. analog comparator the analog comparator compares the input values on the positive pin acmpx and negative pin acmpm. 18.1 overview the at90pwm1 features three fast analog comparators. each comparator has a dedicated input on the positive input, and the negative input can be con - figured as: ? a steady value among the 4 internal reference levels defined by the vref selected thanks to the refs1:0 bits in admux register. ? a value generated from the internal dac ? an external analog input acmpm. when the voltage on the positive acmpn pin is higher than the voltage selected by the acnm multiplexer on the negative input, the analog comparator output, acno, is set. the comparator is a clocked comparator. a new comparison is done on the falling edge of clk i/o or clk i/o /2 ( depending on acckdiv fit of acsr register, see ?analog comparator sta - tus register ? acsr? on page 179. ). each comparator can trigger a separate interrupt, exclusive to the analog comparator. in addi - tion, the user can select interrupt triggering on comparator output rise, fall or toggle. the interrupt flags can also be used to synchronize adc or dac conversions. moreover, the comparator?s output of the comparator 1 can be set to trigger the timer/counter1 input capture function. a block diagram of the three comparators and their surrounding logic is shown in figure 18-1 . 177 4378c?avr?09/08 at90pwm1 figure 18-1. analog comparator block diagram (1)(2) notes: 1. adc multiplexer output: see table 63 on page 195 . 2. refer to figure 3-1 on page 2 and for analog comparator pin placement. 3. the voltage on vref is defined in 62 ?adc voltage reference selection? on page 194 18.2 analog comparator register description each analog comparator has its own control register. a dedicated register has been designed to consign the outputs and the flags of the 3 analog comparators. 18.2.1 analog comparator 0 control register ? ac0con ? bit 7? ac0en: analog comparator 0 enable bit set this bit to enable the analog comparator 0. clear this bit to disable the analog comparator 0. ? bit 6? ac0ie: analog comparator 0 interrupt enable bit set this bit to enable the analog comparator 0 interrupt. clear this bit to disable the analog comparator 0 interrupt. ? bit 5, 4? ac0is1, ac0is0: analog comparator 0 interrupt select bit bit 7 6543210 ac0en ac0ie ac0is1 ac0is0 - ac0m2 ac0m1 ac0m0 ac0con read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0000000 178 4378c?avr?09/08 at90pwm1 these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 56 . ? bit 2, 1, 0? ac0m2, ac0m1, ac0m0: analog comparator 0 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 57 . 18.2.2 analog comparator 2 control register ? ac2con ? bit 7? ac2en: analog comparator 2 enable bit set this bit to enable the analog comparator 2. clear this bit to disable the analog comparator 2. ? bit 6? ac2ie: analog comparator 2 interrupt enable bit set this bit to enable the analog comparator 2 interrupt. clear this bit to disable the analog comparator 2 interrupt. ? bit 5, 4? ac2is1, ac2is0: analog comparator 2 interrupt select bit table 56. interrupt sensitivity selection ac0is1 ac0is0 description 0 0 comparator interrupt on output toggle 0 1 reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 57. analog comparator 0 negative input selection ac0m2 ac0m1 ac0m0 description 000?vref?/6.40 001?vref?/3.20 010?vref?/2.13 011?vref?/1.60 100analog comparator negative input (acmpm pin) 101reserved 110reserved 111reserved bit 7 6543210 ac2en ac2ie ac2is1 ac2is0 ac2m2 ac2m1 ac2m0 ac2con read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0000000 179 4378c?avr?09/08 at90pwm1 these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 56 . ? bit 2, 1, 0? ac2m2, ac2m1, ac2m0: analog comparator 2 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 59 . 18.2.3 analog comparator status register ? acsr ? bit 7? acckdiv: analog comparator clock divider the analog comparators can work with a clock up to 8mhz@3v and 16mhz@5v. set this bit in case the clock frequency of the microcontroller is higher than 8 mhz to insert a divider by 2 between the clock of the microcontroller and the clock of the analog comparators. clear this bit to have the same clock frequency for the microcontroller and the analog comparators. ? bit 6? ac2if: analog comparator 2 interrupt flag bit this bit is set by hardware when comparator 2 output event triggers off the interrupt mode defined by ac2is1 and ac2is0 bits in ac2con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac2ie in ac2con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 5? ac0if: analog comparator 0 interrupt flag bit this bit is set by hardware when comparator 0 output event triggers off the interrupt mode defined by ac0is1 and ac0is0 bits in ac0con register. table 58. interrupt sensitivity selection ac2is1 ac2is0 description 0 0 comparator interrupt on output toggle 0 1 reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 59. analog comparator 2 negative input selection ac2m2 ac2m1 ac2m0 description 000?vref?/6.40 001?vref?/3.20 010?vref?/2.13 011?vref?/1.60 100analog comparator negative input (acmpm pin) 101dac result 110reserved 111reserved bit 7 6 4 3 2 0 acckdiv ac2if ac0if - ac2o ac0o acsr read/write r/w r/w r/w - r r initial value 0 0 0 0 0 0 180 4378c?avr?09/08 at90pwm1 this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac0ie in ac0con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 2? ac2o: analog comparator 2 output bit ac2o bit is directly the output of the analog comparator 2. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 0? ac0o: analog comparator 0 output bit ac0o bit is directly the output of the analog comparator 0. set when the output of the comparator is high. cleared when the output comparator is low. 18.2.4 digital input disable register 0 ? didr0 ? bit 3:2 ? acmpm and acmp2d: acmpm and acmp2 digital input disable when this bit is written logic one, the digital input buffer on the corresponding analog pin is dis - abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 18.2.5 digital input disable register 1? didr1 ? bit 5, 2: acmp0d and acmp1 digital input disable when this bit is written logic one, the digital input buffer on the corresponding analog pin is dis - abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 adc7d adc6d adc5d adc4d adc3d acmpm adc2d acmp2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - acmp0d amp0pd amp0nd didr1 read/write - - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 181 4378c?avr?09/08 at90pwm1 19. analog to digital converter - adc 19.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 8- 250 s conversion time ? up to 120 ksps at maximum resolution ? 11 multiplexed single ended input channels ? two differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40 ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56 v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto triggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler the at90pwm1 features a 10-bit successive approximation adc. the adc is connected to an 15-channel analog multiplexer which allows eleven single-ended input. the single-ended volt - age inputs refer to 0v (gnd). the device also supports 2 differential voltage input combinations which are equipped with a programmable gain stage, providing amplification steps of 14db (5x), 20 db (10x), 26 db (20x), or 32db (40x) on the differential input voltage before the a/d conversion. on the amplified chan - nels, 8-bit resolution can be expected. the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 19-1 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 188 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the voltage refer - ence may be externally decoupled at the aref pin by a capacitor for better noise performance. 182 4378c?avr?09/08 at90pwm1 figure 19-1. analog to digital converter block schematic 183 4378c?avr?09/08 at90pwm1 19.2 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi - mation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference voltage may be con - nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference is set by the refs1 and refs0 bits in admux register, whatever the adc is enabled or not. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented righ t adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completed before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 19.3 starting a conversion a single conversion is started by writing a logi cal one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progre ss and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is started. this provides a method of starting con - versions at fixed intervals. if the trigger signal is still set when the conversion completes, a new conversion will not be started. if another positiv e edge occurs on the trigger signal during con - version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 184 4378c?avr?09/08 at90pwm1 figure 19-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con - stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive conversions independently of whether the adc interrupt flag, adif is cleared or not. the free running mode is not allowed on the amplified channels. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 19.4 prescaling and conversion timing figure 19-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 2 mhz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 2 mhz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100 khz. the prescali ng is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 185 4378c?avr?09/08 at90pwm1 when initiating a single ended conversion by setting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. see ?changing channel or reference selection? on page 186 for details on differential conversion timing. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 3.5 adc clock cycles after the start of a normal conver - sion and 13.5 adc clock cycles after the start of an first conversion. when a conversion is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three addi - tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately after the conversion com - pletes, while adsc remains high. for a summary of conversion times, see table 60 . figure 19-4. adc timing diagram, first conversion (single conversion mode) figure 19-5. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 4 5 6 7 8 9 10 11 12 13 14 15 16 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 1 2 3 186 4378c?avr?09/08 at90pwm1 figure 19-6. adc timing diagram, auto triggered conversion figure 19-7. adc timing diagram, free running conversion 19.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con - tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. table 60. adc conversion time condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of conversion) 13.5 3.5 2 conversion time (cycles) 25 15.5 16 1 2 3 4 5 6 7 8 13 14 15 16 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 14 15 16 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 187 4378c?avr?09/08 at90pwm1 if auto triggering is used, the exact time of the triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during conversion, minimum one adc clock cycle after the trigger event. 3. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. in order to start a conversion on an amplified channel, there is a dedicated adascr bit in adc - srb register which wait for the next amplifier trigger event before really starting the conversion by an hardware setting of the adsc bit in adcsra register. 19.5.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. ? in free running mode, because the amplifier clear the adsc bit at the end of an amplified conversion, it is not possible to use the free running mode, unless adsc bit is set again by soft at the end of each conversion. 19.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is gener - ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 188 4378c?avr?09/08 at90pwm1 if differential channels are used, the selected reference should not be closer to av cc than indi - cated in table 23-5 on page 245 . 19.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adate bit is reset. b. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. c. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. d. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter - ing such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conver - sions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extended conversion to get a valid result. 19.6.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 19-8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard - less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wi th an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped - ance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. 189 4378c?avr?09/08 at90pwm1 figure 19-8. analog input circuitry 19.6.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 19-9 . 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 19-9. adc power connections adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 190 4378c?avr?09/08 at90pwm1 19.6.3 offset compensation schemes the gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea - surements as much as possible. the remaining offset in the analog path can be measured directly by shortening both differential inputs using the ampxis bit with both inputs unconnected. ( see ?amplifier 0 control and status register ? amp0csr? on page 202. ). this offset residue can be then subtracted in software from the measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. 19.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 19-10. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb output code v ref input voltage ideal adc actual adc offset error 191 4378c?avr?09/08 at90pwm1 figure 19-11. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 19-12. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc gain error output code v ref input voltage ideal adc actual adc inl 192 4378c?avr?09/08 at90pwm1 figure 19-13. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 19.7 adc conversion result after the conversion is complete (adif is high), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is: where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 62 on page 194 and table 63 on page 195 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bit is zero, the result is posi - tive. figure 19-14 shows the decoding of the differential input range. table 82 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a reference voltage of v ref . output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? () gain 512 ?? v ref ------------------------------------------------------------------------ = 193 4378c?avr?09/08 at90pwm1 figure 19-14. differential measurement range example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 table 61. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x3ff 0x200 - v ref /gain /gain 194 4378c?avr?09/08 at90pwm1 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. 19.8 adc register description the adc of the at90pwm1 is controlled through 3 different registers. the adcsra and the adcsrb registers which are the adc contro l and status registers, and the admux which allows to select the vref source and the channel to be converted. the conversion result is stored on adch and adcl register which contain respectively the most significant bits and the less significant bits. 19.8.1 adc multiplexer register ? admux ? bit 7, 6 ? refs1, 0: adc vref selection bits these 2 bits determine the voltage reference for the adc. the different setting are shown in table 62 . if these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while the adif bit in adcsra register is set). in case the internal vref is selected, it is turned on as soon as an analog feature needed it is set. ? bit 5 ? adlar: adc left adjust result set this bit to left adjust the adc result. clear it to right adjust the adc result. the adlar bit affects the configuration of the adc result data registers. changing this bit affects the adc data registers immediately regardless of any on going conversion. for a com - plete description of this bit, see section ?adc result data registers ? adch and adcl?, page 198 . bit 7 6543210 refs1 refs0 adlar - mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w - r/w r/w r/w r/w initial value 0 0000000 table 62. adc voltage reference selection refs1 refs0 description 0 0 external vref on aref pin, internal vref is switched off 0 1 avcc with external capacitor connected on the aref pin 1 0 reserved 11 internal 2.56v reference voltage with external capacitor connected on the aref pin 195 4378c?avr?09/08 at90pwm1 ? bit 3, 2, 1, 0 ? mux3, mux2, mux1, mux0: adc channel selection bits these 4 bits determine which analog inputs are connected to the adc input. the different set - ting are shown in table 63 . if these bits are changed during a conversion, the change will not take effect until this conversion is complete (it means while the adif bit in adcsra register is set). 19.8.2 adc control and status register a ? adcsra ? bit 7 ? aden: adc enable bit set this bit to enable the adc. clear this bit to disable the adc. clearing this bit while a conversion is running will take effect at the end of the conversion. ? bit 6? adsc: adc start conversion bit set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. cleared by hardware when the conversion is complete. writing this bit to zero has no effect. the first conversion performs the initialization of the adc. in order to start a conversion on an amplified channel with the at90pwm1, use the adcs bit in adcsra register. table 63. adc input channel selection mux3 mux2 mux1 mux0 description 0000adc0 0001adc1 0010adc2 0011adc3 0100adc4 0101adc5 0110adc6 0111adc7 1000reserved 1001reserved 1010reserved 1011amp0 1100reserved 1101reserved 1 1 1 0 bandgap 1111gnd bit 7 6543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0000000 196 4378c?avr?09/08 at90pwm1 ? bit 5 ? adate: adc auto trigger enable bit set this bit to enable the auto triggering mode of the adc. clear it to return in single conversion mode. in auto trigger mode the trigger source is selected by the adts bits in the adcsrb register. see table 19-1 on page 197 . ? bit 4? adif: adc interrupt flag set by hardware as soon as a conversion is complete and the data register are updated with the conversion result. cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif can be cleared by writing it to logical one. ? bit 3? adie: adc interrupt enable bit set this bit to activate the adc end of conversion interrupt. clear it to disable the adc end of conversion interrupt. ? bit 2, 1, 0? adps2, adps1, adps0: adc prescaler selection bits these 3 bits determine the division factor between the system clock frequency and input clock of the adc. the different setting are shown in table 64 . 19.8.3 adc control and status register b? adcsrb ? bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. set this bit if you wish to convert with an adc clock frequency higher than 200khz. ? bit 3, 2, 1, 0? adts3:adts0: adc auto trigger source selection bits these bits are only necessary in case the adc works in auto trigger mode. it means if adate bit in adcsra register is set. in accordance with the table 19-1, these 3 bits select the interrupt event which will generate the trigger of the start of conversion. the start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. in case of trig on pscnasy table 64. adc prescaler selection adps2 adps1 adps0 division factor 0002 0012 0104 0118 10016 10132 11064 111128 bit 7 6543210 adhsm - - adascr adts3 adts2 adts1 adts0 adcsrb read/write - - - r/w r/w r/w r/w r/w initial value 0 0000000 197 4378c?avr?09/08 at90pwm1 event, there is no flag. so in this case a c onversion will start each ti me the trig event appears and the previous conversion is completed table 19-1. adc auto trigger source selection for non amplified conversions adts3 adts2 adts1 adts0 description 0 0 0 0 free running mode 0 0 0 1 analog comparator 0 0 0 1 0 external interrupt request 0 0 0 1 1 timer/counter0 compare match 0 1 0 0 timer/counter0 overflow 0 1 0 1 timer/counter1 compare match b 0 1 1 0 timer/counter1 overflow 0 1 1 1 timer/counter1 capture event 1 0 0 0 psc0asy event (1) 1. for trigger on any psc event, if the psc uses the pll clock, the core must use pll/4 clock source. 1001reserved 1 0 1 0 psc2asy event (1) 1 0 1 1 analog comparator 1 1 1 0 0 analog comparator 2 1101reserved 1110reserved 1111reserved table 19-2. adc auto trigger source selection for amplified conversions adts3 adts2 adts1 adts0 description 0 0 0 0 free running mode 0001reserved 0010reserved 0011reserved 0100reserved 0101reserved 0110reserved 0111reserved 1 0 0 0 psc0asy event (1) 1001reserved 1 0 1 0 psc2asy event (1) 1011reserved 198 4378c?avr?09/08 at90pwm1 19.8.4 adc result data registers ? adch and adcl when an adc conversion is complete, the conversion results are stored in these two result data registers. when the adcl register is read, the two adc result data registers can?t be updated until the adch register has also been read. consequently, in 10-bit configuration, the adcl register must be read first before the adch. nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the adlar bit in the adcsra register. like this, it is sufficient to only read adch to have the conversion result. 19.8.4.1 adlar = 0 1100reserved 1101reserved 1110reserved 1111reserved 1. for trigger on any psc event, if the psc uses the pll clock, the core must use pll/4 clock source. table 19-2. adc auto trigger source selection for amplified conversions adts3 adts2 adts1 adts0 description bit 7 6543210 - - - - - - adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl read/write rrrrrrrr rrrrrrrr initial value0 0000000 0 0000000 199 4378c?avr?09/08 at90pwm1 19.8.4.2 adlar = 1 19.8.5 digital input disable register 0 ? didr0 ? bit 7:0 ? adc7d..adc0d: acmp2:1 and adc7:0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is dis - abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 19.8.6 digital input disable register 1? didr1 ? bit 5:0 ? acmp0d, amp0+d, amp0-d, adc10d..adc8d: acmp0, amp1:0 and adc10:8 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is dis - abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 19.9 amplifier the at90pwm1 features one differential amplified channel with programmable 5, 10, 20, and 40 gain stage. on at90pwm1, the amplifier has been improved in order to speed-up the conversion time.the proposed improvement takes advantage of the amplifier characteristics to ensure a conversion in less time. in order to have a better understanding of the functioning of the amplifier synchronization, a tim - ing diagram example is shown figure 19-16 for at90pwm1. as soon as a conversion is requested thanks to the adsc bit, the analog to digital conversion is started. in case the amplifier output is modified during the sample phase of the adc, the on- going conversion is aborted and restarted as soon as the output of the amplifier is stable. this ensure a fast response time. the only precaution to take is to be sure that the trig signal (psc) frequency is lower than adcclk/4. bit 7 6543210 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 - -----adcl read/write rrrrrrrr rrrrrrrr initial value0 0000000 0 0000000 bit 76543210 adc7d adc6d adc5d adc4d adc3d acmpm adc2d acmp2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - - acmp0d amp0pd amp0nd didr1 read/write - - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 200 4378c?avr?09/08 at90pwm1 figure 19-15. amplifier synchronization timing diagram f with change on analog input signal valid sample delta v 4th stable sample signal to be measured ampli_clk (sync clock) ck adc ps cn_asy psc block adsc adc activity adc adc sampling adc co n v adc sampling adc co n v adc result ready adc result ready 201 4378c?avr?09/08 at90pwm1 figure 19-16. amplifier synchronization timing diagram adsc is set when the amplifier output is changing due to the amplifier clock switch. the block diagram of the amplifier is shown on figure 19-17 . valid sample signal to be measured ampli_clk (sync clock) ck adc ps cn_asy psc block adsc adc activity adc adc sampling adc co n v adc sampling adc co n v adc sampling abort ed adc result ready adc result ready 202 4378c?avr?09/08 at90pwm1 figure 19-17. amplifiers block diagram 19.10 amplifier control registers the configuration of the amplifiers are controlled via two dedicated registers amp0csr and amp1csr. then the start of conversion is done via the adc control and status registers. the conversion result is stored on adch and adcl register which contain respectively the most significant bits and the less significant bits. 19.10.1 amplifier 0 control and status register ? amp0csr ? bit 7 ? amp0en: amplifier 0 enable bit set this bit to enable the amplifier 0. clear this bit to disable the amplifier 0. clearing this bit while a conversion is running will take effect at the end of the conversion. warning: always clear amp0ts1:0 when clearing amp0en. ? bit 6? amp0is: amplifier 0 input shunt set this bit to short-circuit the amplifier 0 input. clear this bit to normally use the amplifier 0. ? bit 5, 4? amp0g1, 0: amplifier 0 gain selection bits bit 7 6543210 amp0en amp0is amp0g1 amp0g0 - - amp0ts1 amp0ts0 amp0csr read/write r/w r/w r/w r/w - - r/w r/w initial value 0 0000000 203 4378c?avr?09/08 at90pwm1 these 2 bits determine the gain of the amplifier 0. the different setting are shown in table 19-3 . to ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 amplifier synchronization clock periods. ? bit 1, 0? amp0ts1, amp0ts0: amplifier 0 trigger source selection bits in accordance with the table 19-4, these 2 bits select the ev ent which will generate the trigger for the amplifier 0. this trigger source is necessary to start the conversion on the amplified channel. table 19-3. amplifier 0 gain selection amp0g1 amp0g0 description 0 0 gain 5 0 1 gain 10 1 0 gain 20 1 1 gain 40 table 19-4. amp0 auto trigger source selection amp0ts1 amp0ts0 description 0 0 auto synchronization on adc clock/8 0 1 trig on psc0asy 10reserved 1 1 trig on psc2asy 204 4378c?avr?09/08 at90pwm1 20. debugwire on-chip debug system 20.1 features ? complete program flow control ? emulates all on-chip functions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of program break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 20.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 20.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu - nication gateway between target and emulator. figure 20-1. the debugwire setup figure 20-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. when designing a system where debugwire will be used, the following observations must be made for correct operation: dw gnd dw(reset) vcc 1.8 - 5.5v 205 4378c?avr?09/08 at90pwm1 ? pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. ? capacitors connected to the reset pin must be disconnected when using debugwire. ? all external reset sources must be disconnected. 20.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the program memory. the instruc - tion replaced by the break instruction will be stored. when program execution is continued, the stored instruction will be executed before continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio through the debugwire interface. the use of break points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 20.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/o functions when running at full speed, i.e., when the program in the cpu is running. when the cpu is stopped, care must be taken while accessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enables some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 20.6 debugwire related register in i/o memory the following section describes the registers used with the debugwire. 20.6.1 debugwire data register ? dwdr the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. 21. boot loader support ? read-w hile-write self-programming in at90pwm1, the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated proto - col to read code and write (program) that code into the flash memory, or read the code from the bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 206 4378c?avr?09/08 at90pwm1 program memory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different levels of protection. 21.1 boot loa der features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 83 on page 225 ) used during programming. the page organization does not affect normal operation. 21.2 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 21-2 ). the size of the different sections is configured by the bootsz fuses as shown in table 70 on page 218 and figure 21-2 . these two sections can have different level of protection since they have different sets of lock bits. 21.2.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 66 on page 210 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 21.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft - ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 67 on page 210 . 21.3 read-while-write and no re ad-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft - ware update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write (rww) section and the no read-while- write (nrww) section. the limit between the rww- and nrww sections is given in table 71 on page 218 and figure 21-2 on page 209 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section dur - ing a boot loader software operation. the syntax ?read-while-write section? refers to which 207 4378c?avr?09/08 at90pwm1 section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 21.3.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should eith er be disabled or moved to the boot loader sec - tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory control and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is com - pleted, the rwwsb must be cleared by software before reading code located in the rww section. see ?store program memory control and status register ? spmcsr? on page 211. for details on how to clear rwwsb. 21.3.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 65. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 208 4378c?avr?09/08 at90pwm1 figure 21-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 209 4378c?avr?09/08 at90pwm1 figure 21-2. memory sections note: 1. the parameters in the figure above are given in table 70 on page 218 . 21.4 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 66 and table 67 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash mem - ory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 210 4378c?avr?09/08 at90pwm1 note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 21.5 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applica - tion code is loaded, the program can start executi ng the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is pro - grammed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 66. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 67. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 68. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 70 on page 218 ) 211 4378c?avr?09/08 at90pwm1 21.5.1 store program memory control and status register ? spmcsr the store program memory control and status register contains the control bits needed to con - trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi - ated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alternatively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the at90pwm1 and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww section, the user software must wait until the programming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is writ - ten while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles after blbset and spmen are set in the spmcsr reg - ister, will read either the lock bits or the fu se bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 215 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 212 4378c?avr?09/08 at90pwm1 data in r1 and r0 are ignored. the pgers bit will auto-clear upon completion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: self programming enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt or pgers, the following spm instruction will have a spe - cial meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 21.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 83 on page 225 ), the program counter can be treated as having two different sections. one sectio n, consisting of the l east significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is1 shown in figure 21-3 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program - ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. bit 15 14 13 12 11 10 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7 z6 z5 z4 z3 z2 z1 z0 7 6 5 4 3 2 1 0 213 4378c?avr?09/08 at90pwm1 figure 21-3. addressing the flash during spm (1) note: 1. the different variables used in figure 21-3 are listed in table 72 on page 219 . 21.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the buffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter - native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 216 for an assembly code example. program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 214 4378c?avr?09/08 at90pwm1 21.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 21.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page writ e operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 21.7.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 21.7.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in xxxxxxxx. 21.7.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 21.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in xxxxxxx, or the interrupts must be disabled. before addressing the rww sec - tion after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 216 for an example. 215 4378c?avr?09/08 at90pwm1 21.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that may prevent the application and boot loader section from any soft - ware update by the mcu. see table 66 and table 67 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when pro - gramming the lock bits the entire flash can be read during the operation. 21.7.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 21.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruc - tion is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blb - set and spmen are cleared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 76 on page 221 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc - tion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be loaded in the destination register as shown below. refer to table 77 on page 222 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the bit 7 6 5 4 3 2 1 0 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 7 6 5 4 3 2 1 0 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 7 6 5 4 3 2 1 0 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 7 6 5 4 3 2 1 0 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 216 4378c?avr?09/08 at90pwm1 value of the extended fuse byte (efb) will be loaded in the destination register as shown below. refer to table 76 on page 221 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 21.7.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating volt- age matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 21.7.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 69 shows the typical pro - gramming time for flash accesses from the cpu. 21.7.12 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot bit 7 6 5 4 3 2 1 0 rd ? ? ? ? efb3 efb2 efb1 efb0 table 69. spm programming time symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 217 4378c?avr?09/08 at90pwm1 ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 219 4378c?avr?09/08 at90pwm1 for details about these two section, see ?nrww ? no read-while-write section? on page 207 and ?rww ? read-while-write section? on page 207 note: 1. z15:z13: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 212 for details about the use of z-pointer during self-programming. 22. memory programming 22.1 program and data memory lock bits the at90pwm1 provides six lock bits which can be left unprogrammed (?1?) or can be pro - grammed (?0?) to obtain the additional features listed in table 74 . the lock bits can only be erased to ?1? with the chip erase command. table 72. explanation of different variables used in figure 21-3 and the mapping to the z- pointer variable corresponding z-value (1) description pcmsb 11 most significant bit in the program counter. (the program counter is 12 bits pc[11:0]) pagemsb 4 most significant bit which is used to address the words within one page (32 words in a page requires 5 bits pc [4:0]). zpcmsb z12 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z5 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[11:5] z12:z6 program counter page address: page select, for page erase and page write pcword pc[4:0] z5:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) table 73. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) 220 4378c?avr?09/08 at90pwm1 notes: 1. ?1? means unprogrammed, ?0? means programmed. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 74. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) table 75. lock bit protection modes (1)(2) . only atmega88/168. blb0 mode blb02 blb01 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 221 4378c?avr?09/08 at90pwm1 22.2 fuse bits the at90pwm1 has three fuse bytes. table 76 - table 78 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logi - cal zero, ?0?, if they are programmed. note: 1. the default value of bootsz1..0 results in maximum boot size. see table 79 on page 224 for details. 22.3 psc output beha viour during reset for external component safety reason, the state of psc outputs during reset can be pro - grammed by fuses pscrv, psc0rb, psc1rb & psc2rb. these fuses are located in the extended fuse byte ( see table 76 ) pscrv gives the state low or high which will be forced on psc outputs selected by psc0rb, psc2rb fuses. if pscrv fuse equals 0 (programmed), the selected psc outputs will be forced to low state. if pscrv fuse equals 1 (unprogrammed), the selected psc outputs will be forced to high state. if psc0rb fuse equals 1 (unprogrammed), pscout00 & pscout01 keep a standard port behaviour. if psc0rb fuse equals 0 (programmed), pscout00 & pscout01 are forced at reset to low level or high level according to pscrv fuse bit. in this second case, pscout00 & pscout01 keep the forced state until psoc0 register is written.. if psc2rb fuse equals 1 (unprogrammed), pscout20, pscout21, pscout22 & pscout23 keep a standard port behaviour. if psc1rb fuse equals 0 (programmed), pscout20, pscout21, pscout22 & pscout23 are forced at reset to low level or high level according to pscrv fuse bit. in this second case, pscout20, pscout21, pscout22 & pscout23 keep the forced state until psoc2 register is written. table 76. extended fuse byte extended fuse byte bit no description default value psc2rb 7 psc2 reset behaviour 1 psc0rb 5 psc0 reset behaviour 1 pscrv 4 pscout reset value 1 ?3? 1 bootsz1 2 select boot size (see table 113 for details) 0 (programmed) (1) bootsz0 1 select boot size (see table 113 for details) 0 (programmed) (1) bootrst 0 select reset vector 1 (unprogrammed) 222 4378c?avr?09/08 at90pwm1 notes: 1. see ?alternate port functions? on page 63 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?watchdog timer configuration? on page 51 for details. 4. see table 9-2 on page 45 for bodlevel fuse decoding. note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 7-10 on page 34 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8 mhz. see table 7-10 on page 34 for details. 3. the ckout fuse allows the system clock to be output on portb0. see ?clock output buffer? on page 35 for details. 4. see ?system clock prescaler? on page 35 for details. the status of the fuse bits is not affected by ch ip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 22.3.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. table 77. fuse high byte high fuse byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) table 78. fuse low byte low fuse byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 223 4378c?avr?09/08 at90pwm1 22.4 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the at90pwm1 the signature bytes are: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x93 (indicates 8kb flash memory). 3. 0x002: 0x83 (indicates at90pwm1 device when 0x001 is 0x93). 22.5 calibration byte the at90pwm1 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this byte is auto - matically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. 22.6 parallel programming parame ters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90pwm1. pulses are assumed to be at least 250 ns unless otherwise noted. 22.6.1 signal names in this section, some pins of the at90pwm1 are referenced by signal names describing their functionality during parallel programming, see figure 22-1 and table 79 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 81 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 82 . figure 22-1. parallel programming vcc gnd xtal1 xa0 rdy/bsy oe reset + 5v avcc + 5v pd1 + 12 v pd7 pd6 pd5 pd4 pd3 pd2 pe2 wr xa1 bs2 pagel bs1 data pb[7:0] 224 4378c?avr?09/08 at90pwm1 table 79. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load bs2 pe2 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) data pb[7:0] i/o bi-directional data bus (output when oe is low) table 80. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 81. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 82. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 225 4378c?avr?09/08 at90pwm1 22.7 serial programming pin mapping 22.8 parallel programming 22.8.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) > programming mode: 1. set prog_enable pins listed in table 80. to ?0000?, reset pin to ?0? and vcc to 0v. 2. apply 4.5 - 5.5v between vcc and gnd. ensure that vcc reaches at least 1.8v within the next 20s. 3. wait 20 - 60s, and apply 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300s before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. if the rise time of the vcc is unable to fulfill the requirements listed above, the following alterna - tive algorithm can be used. 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 83. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb at90pwm1 4k words (8k bytes) 32 words pc[4:0] 128 pc[11:5] 11 table 84. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb at90pwm1 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 table 82. command byte bit coding command byte command executed table 85. pin mapping serial programming symbol pins i/o description mosi_a pd3 i serial data in miso_a pd2 o serial data out sck_a pd4 i serial clock 226 4378c?avr?09/08 at90pwm1 1. set prog_enable pins listed in table 80. to ?0000?, reset pin to ?0? and vcc to 0v. 2. apply 4.5 - 5.5v between vcc and gnd. 3. monitor vcc, and as soon as vcc reaches 0.9 - 1.1v, apply 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait until vcc actually reaches 4.5 -5.5v before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. 22.8.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 22.8.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 22.8.4 programming the flash the flash is organized in pages, see table 83 on page 225 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro - grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 227 4378c?avr?09/08 at90pwm1 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 22-3 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 22-2 on page 228 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 22-3 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. 228 4378c?avr?09/08 at90pwm1 figure 22-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 83 on page 225 . figure 22-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. 22.8.5 programming the eeprom the eeprom is organized in pages, see table 84 on page 225 . when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algo rithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 226 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 229 4378c?avr?09/08 at90pwm1 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts programming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 22-4 for signal waveforms). figure 22-4. programming the eeprom waveforms 22.8.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 226 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 22.8.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 226 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 230 4378c?avr?09/08 at90pwm1 22.8.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 226 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 22.8.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 226 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 22.8.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 226 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 22-5. programming the fuses waveforms 22.8.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 226 for details on command and data loading): rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 231 4378c?avr?09/08 at90pwm1 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 22.8.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 226 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 22-6. mapping between bs1, bs2 and the fuse and lock bits during read 22.8.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 226 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 22.8.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 226 for details on command and address loading): lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 232 4378c?avr?09/08 at90pwm1 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 22.8.15 parallel programming characteristics figure 22-7. parallel programming timing, including some general timing requirements figure 22-8. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 22-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) 233 4378c?avr?09/08 at90pwm1 figure 22-9. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 22-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to read- ing operation. table 86. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 234 4378c?avr?09/08 at90pwm1 notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 22.9 serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out - put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 85 on page 225 , the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. figure 22-10. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 1.8 - 5.5v when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 22.9.1 serial programming algorithm when writing serial data to the at90pwm1, data is clocked on the rising edge of sck. t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 86. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min typ max units vcc gnd xtal1 sck_a miso_a mosi_a reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 235 4378c?avr?09/08 at90pwm1 when reading data from the at90pwm1, data is clocked on the falling edge of sck. see figure 22-11 for timing details. to program and verify the at90pwm1 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 88 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if the communication is out of synchro- nization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 8 msb of the address. if polling is not used, the user must wait at least t wd_flash before issuing the next page. (see table 87 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 87 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the con- tent at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. 22.9.2 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at the time the device is ready for a new page, the programmed value will read correctly. this is used to determine when the next page can be writ - ten. note that the entire page is written simultaneously and any address within the page can be used for polling. data polling of the flash will not work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. see table 87 for t wd_flash value. 22.9.3 data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being programmed will give the value 0xff. at the time the device is ready for 236 4378c?avr?09/08 at90pwm1 a new byte, the programmed value will read correctly. this is used to determine when the next byte can be written. this will not work for the value 0xff, but the user should have the following in mind: as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re-pro - grammed without chip erasing the device. in this case, data polling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 87 for t wd_eeprom value. figure 22-11. serial programming waveforms table 87. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 3.6 ms t wd_erase 9.0 ms msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output table 88. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 000 a aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx xx bb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 000 a aaaa bb xx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x xx aa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x xx aa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . 237 4378c?avr?09/08 at90pwm1 note: a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care 22.9.4 spi serial programming characteristics for characteristics of the spi module see ?spi serial programming characteristics? on page 237 . load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 00xx xx aa bbbb bb00 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 73 on page 219 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 73 on page 219 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table xxx on page xxx for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 77 on page 222 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii set bits = ?0? to program, ?1? to unprogram. see table 76 on page 221 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table xxx on page xxx for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 77 on page 222 for details. read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 76 on page 221 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 88. serial programming instruction set (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte4 238 4378c?avr?09/08 at90pwm1 23. electrical characteristics (1) 23.1 absolute maximum ratings* note: 1. electrical characteristics for this product have not yet been finalized. please consider all val- ues listed herein as preliminary and non-contractual. operating temperature.................................. -40 c to +105 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-1.0v to v cc +0.5v voltage on reset with respect to ground......-1.0v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma 239 4378c?avr?09/08 at90pwm1 23.2 dc characteristics t a = -40 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage port b, c & d and xtal1, xtal2 pins as i/o -0.5 0.2v cc (1) v v ih input high voltage port b, c & d and xtal1, xtal2 pins as i/o 0.6v cc (2) v cc +0.5 v v il1 input low voltage xtal1 pin , external clock selected -0.5 0.1v cc (1) v v ih1 input high voltage xtal1 pin , external clock selected 0.7v cc (2) v cc +0.5 v v il2 input low voltage reset pin -0.5 0.2v cc (1) v v ih2 input high voltage reset pin 0.9v cc (2) v cc +0.5 v v il3 input low voltage reset pin as i/o -0.5 0.2v cc (1) v v ih3 input high voltage reset pin as i/o 0.8v cc (2) v cc +0.5 v v ol output low voltage (3) (port b, c & d and xtal1, xtal2 pins as i/o) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v v oh output high voltage (4) (port b, c & d and xtal1, xtal2 pins as i/o) i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.4 v v v ol3 output low voltage (3) (reset pin as i/o) i ol = 2.1 ma, v cc = 5v i ol = 0.8 ma, v cc = 3v 0.7 0.5 v v v oh3 output high voltage (4) (reset pin as i/o) i oh = -0.6 ma, v cc = 5v i oh = -0.4 ma, v cc = 3v 3.8 2.2 v v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 200 k r pu i/o pin pull-up resistor 20 50 k 240 4378c?avr?09/08 at90pwm1 note: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where the pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: so32, so24 and tqfn package: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for ports b6 - b7, c0 - c1, d0 - d3, e0 should not exceed 100 ma. 3] the sum of all iol, for ports b0 - b1, c2 - c3, d4, e1 - e2 should not exceed 100 ma. 4] the sum of all iol, for ports b3 - b5, c6 - c7 should not exceed 100 ma. 5] the sum of all iol, for ports b2, c4 - c5, d5 - d7 should not exceed 100 ma. if iol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20 ma at vcc = 5v, 10 ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: so32, so24 and tqfn package: 1] the sum of all ioh, for all ports, should not exceed 400 ma. 2] the sum of all ioh, for ports b6 - b7, c0 - c1, d0 - d3, e0 should not exceed 150 ma. 3] the sum of all ioh, for ports b0 - b1, c2 - c3, d4, e1 - e2 should not exceed 150 ma. 4] the sum of all ioh, for ports b3 - b5, c6 - c7 should not exceed 150 ma. 5] the sum of all ioh, for ports b2, c4 - c5, d5 - d7 should not exceed 150 ma. if ioh exceeds the test condition, voh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. i cc power supply current active 8 mhz, v cc = 3v, rc osc, prr = 0xff 3.8 7 ma active 16 mhz, v cc = 5v, ext clock, prr = 0xff 14 24 ma idle 8 mhz, v cc = 3v, rc osc 1.5 3 ma idle 16 mhz, v cc = 5v, ext clock 5.5 10 ma power-down mode (5) wdt enabled, v cc = 3v t0 < 90c 515a wdt enabled, v cc = 3v t0 < 105c 920a wdt disabled, v cc = 3v t0 < 90c 23a wdt disabled, v cc = 3v t0 < 105c 510a v acio analog comparator input offset voltage at90pwm2/3 v cc = 5v, v in = 3v 20 50 mv v hysr analog comparator hysteresis voltage at90pwm2b/3b v cc = 5v, v in = 3v rising edge falling edge 33 34 46 62 71 110 mv mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 5.0v (6) (6) ns t a = -40 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units 241 4378c?avr?09/08 at90pwm1 5. minimum v cc for power-down is 2.5v. 6. the analog comparator propogation dela y equals 1 comparator clock plus 30 ns. see ?analog comparator? on page 176. for comparator clock definition. 23.3 external clock drive characteristics 23.3.1 calibrated internal rc oscillator accuracy 23.3.2 external clock drive waveforms figure 23-1. external clock drive waveforms 23.3.3 external clock drive table 23-1. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0 mhz 3v 25 c 10% user calibration 7.3 - 8.1 mhz 2.7v - 5.5v -40 c - 85 c1% v il1 v ih1 table 23-2. external clock drive symbol parameter v cc =1.8-5.5v v cc =2.7-5.5v v cc =4.5-5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 04010020mhz t clcl clock period 250 100 50 ns t chcx high time 100 40 20 ns t clcx low time 100 40 20 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 2% 242 4378c?avr?09/08 at90pwm1 23.4 maximum speed vs. v cc maximum frequency is depending on v cc. as shown in figure 23-2 , the maximum frequency equals 8mhz when v cc is contained between 2.7v and 4.5v and equals 16mhz when v cc is contained between 4.5v and 5.5v. figure 23-2. maximum frequency vs. v cc , at90pwm1 23.5 pll characteristics . note: while connected to external clock or external oscillator, pll input frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (cpu core, psc...) safe operating area 16mhz 8mhz 2.7v 5.5v 4.5v table 23-3. pll characteristics - v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter min. typ. max. units pll if input frequency 0.5 1 2 mhz pll f pll factor 64 pll lt lock-in time 64 s 243 4378c?avr?09/08 at90pwm1 23.6 spi timing characteristics see figure 23-3 and figure 23-4 for details. note: in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck >12 mhz figure 23-3. spi interface timing requirements (master mode) table 23-4. spi timing parameters description mode min. typ. max. 1 sck period master see table 54 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 244 4378c?avr?09/08 at90pwm1 figure 23-4. spi interface timing requirements (slave mode) mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 245 4378c?avr?09/08 at90pwm1 23.7 adc characteristics table 23-5. adc characteristics - t a = -40 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min typ max units resolution single ended conversion 10 bits differential conversion 8 bits absolute accuracy single ended conversion v ref = 2.56v adc clock = 500 khz 2.5 3 lsb single ended conversion v ref = 2.56v adc clock = 1mhz 6 (*) 7 lsb single ended conversion v ref = 2.56v adc clock = 2mhz 20 lsb differential conversion v ref = 2.56v adc clock = 500 khz 23lsb differential conversion v ref = 2.56v adc clock = 1mhz 3 (1) 4lsb integral non-linearity single ended conversion v cc = 4.5v, v ref = 2.56v adc clock = 1mhz 1.1 1.5 lsb single ended conversion v cc = 4.5v, v ref = 2.56v adc clock = 500 khz 0.6 1 lsb differential conversion v cc = 4.5v, v ref = 2.56v adc clock = 1mhz 1.5 2 lsb differential conversion v cc = 4.5v, v ref = 2.56v adc clock = 500 khz 11.5lsb differential non-linearity single ended conversion v cc = 4.5v, v ref = 4v adc clock = 1mhz 0.4 0.6 lsb single ended conversion v cc = 4.5v, v ref = 4v adc clock = 500 khz 0.3 0.5 lsb differential conversion v cc = 4.5v, v ref = 4v adc clock = 1mhz 0.5 0.8 lsb differential conversion v cc = 4.5v, v ref = 4v adc clock = 500 khz 0.4 0.8 lsb 246 4378c?avr?09/08 at90pwm1 notes: 1. on at90pwm2b/3b, this value will be close to the value at 500khz. 2. 125khz when input signal is synchronous with amplifier clock. zero error (offset) single ended conversion v cc = 4.5v, v ref = 4v adc clock = 1mhz -4 0 lsb single ended conversion v cc = 4.5v, v ref = 4v adc clock = 500 khz -2 2.5 lsb differential conversion v cc = 4.5v, v ref = 4v adc clock = 1mhz -0.5 -0.5 lsb differential conversion v cc = 4.5v, v ref = 4v adc clock = 500 khz -0.5 -0.5 lsb conversion time single conversion 8 320 s clock frequency 50 2000 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage single ended conversion 2.0 av cc v differential conversion 2.0 av cc - 0.2 v v in input voltage single ended conversion gnd v ref differential conversion -v ref /gain +v ref /gain input bandwidth single ended conversion 38.5 khz differential conversion 4 (2) khz v int internal voltage reference 2.56 v r ref reference input resistance 30 k r ain analog input resistance 100 m i hsm increased current consumption high speed mode single ended conversion 380 a table 23-5. adc characteristics - t a = -40 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min typ max units 247 4378c?avr?09/08 at90pwm1 23.8 parallel programming characteristics figure 23-5. parallel programming timing, including some general timing requirements figure 23-6. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 23-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) 248 4378c?avr?09/08 at90pwm1 figure 23-7. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. ggthe timing requirements shown in figure 23-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz table 23-6. parallel programming characteristics, v cc = 5v 10% symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 10 ms 249 4378c?avr?09/08 at90pwm1 notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 24. at90pwm1 typical characteristics the following charts show typical behavior. these figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the analog comparator is dis - abled during these measurements. table 24-1 on page 254 and table 24-2 on page 254 show the additional current consumption compared to i cc active and i cc idle for every i/o module con - trolled by the power reduction register. see ?power reduction register? on page 37 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient tempera - ture. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential cur - rent drawn by the watchdog timer. t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 23-6. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min. typ. max. units 250 4378c?avr?09/08 at90pwm1 24.1 active supply current figure 24-1. active supply current vs. frequency (0.1 - 1.0 mhz) figure 24-2. active supply current vs. frequency (1 - 24 mhz) active supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) active supply current vs. frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 5 10 15 20 25 30 0 5 10 15 20 25 frequency (mhz) i cc (ma) 251 4378c?avr?09/08 at90pwm1 figure 24-3. active supply current vs. v cc (internal rc oscillator, 8 mhz) figure 24-4. active supply current vs. v cc (internal pll oscillator, 16 mhz) active supply current vs. v cc interna l rc oscilla tor, 8 mhz 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 22,533,544,555,5 v cc (v) i cc (ma) active supply current vs. v cc internal pll oscillator, 16 mhz 105 c 85 c 25 c -40 c 0 2 4 6 8 10 12 14 16 18 20 22,533,544,555,5 v cc (v) i cc (ma) 252 4378c?avr?09/08 at90pwm1 24.2 idle supply current figure 24-5. idle supply current vs. frequency (0.1 - 1.0 mhz) figure 24-6. idle supply current vs. frequency (1 - 24 mhz) idle supply current vs. low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0,45 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) idle supply current vs. frequency 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 -1 1 3 5 7 9 11 13 15 17 19 21 23 25 frequency (mhz) i cc (ma) 253 4378c?avr?09/08 at90pwm1 figure 24-7. iidle supply current vs. v cc (internal rc oscillator, 8 mhz) figure 24-8. idle supply current vs. v cc (internal pll oscillator, 16 mhz) 24.2.1 using the power reduction register the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules idle supply current vs. v cc interna l rc oscilla tor, 8 mhz 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) idle supply current vs. v cc interna l pll oscilla tor, 16 mhz 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 254 4378c?avr?09/08 at90pwm1 are controlled by the power reduction register. see ?power reduction register? on page 39 for details. it is possible to calculate the typical current consumption based on the numbers from table 24-2 for other v cc and frequency settings than listed in table 24-1 . 24.2.1.1 example 1 calculate the expected current consumption in idle mode with usart, timer1, and spi enabled at v cc = 3.0v and f = 1mhz. from table 24-2 , third column, we see that we need to add 18% for the usart, 26% for the spi, and 11% for the timer1 module. reading from fig- ure 24-5 , we find that the idle current consumption is ~0,17ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with usart0, timer1, and spi enabled, gives: 24.2.1.2 example 2 same conditions as in example 1, but in active mode instead. from table 24-2 , second column we see that we need to add 3.3% for the usart, 4.8% for the spi, and 2.0% for the timer1 module. reading from figure 24-1 , we find that the active current consumption is ~0,6ma at v cc table 24-1. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 3v, f = 8mhz v cc = 5v, f = 16mhz prpsc2 350 ua 1.3 ma prpsc1 350 ua 1.3 ma prpsc0 350 ua 1.3 ma prtim1 300 ua 1.15 ma prtim0 200 ua 0.75 ma prspi 250 ua 0.9 ma prusart 550 ua 2 ma pradc 350 ua 1.3 ma table 24-2. additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 24-1 and figure 24-2 ) additional current consumption compared to idle with external clock (see figure 24-5 and figure 24-6 ) prpsc2 10% 25% prpsc1 10% 25% prpsc0 10% 25% prtim1 8.5% 22% prtim0 4.3% 11% prspi 5.3% 14% prusart 15.6 36 pradc 10.5% 25% i cc total 0.17 ma 10.360.220.14 +++ () ? 0.29 ma ? 255 4378c?avr?09/08 at90pwm1 = 3.0v and f = 1mhz. the total current consumption in idle mode with usart, timer1, and spi enabled, gives: 24.2.1.3 example 3 all i/o modules should be enabled. calculate the expected current consumption in active mode at v cc = 3.6v and f = 10mhz. we find the active current consumption without the i/o modules to be ~ 7.0ma (from figure 24-2 ). then, by using the numbers from table 24-2 - second column, we find the total current consumption: 24.2.2 power consumption estimation with clock prescaling curves on figure 24-1 , figure 24-2 , figure 24-5 and figure 24-6 are measured with an external clock source and provides the power consumption of the microcontroller core at a given frequency. the total power consumption of the microcontroller comes from the clock tree shown on figure 7-1 on page 27 , thus it is the sum of the following terms: ? oscillator ? pll if used ? clock prescaler ? core ? peripheral ? i/o when using the clock prescaler clkpr to reduce the frequency ( see ?system clock prescaler? on page 35. ), the power consumption of the oscillators and the prescaler can became the domi- nant factor of the active and idle power consumption. typical power consumption of the oscillators is given on table 24-3 . i cc total 0.6 ma 1 0.156 0.085 0.053 +++ () ? 0.77 ma ? ma 1 0.1 0.1 0.1 0.085 0.043 0.053 0.156 0.105 ++++++++ () ? 12.2 ma ? table 24-3. power consumption of the clock system block mhz typical numbers a v cc = 3v v cc = 5v watch dog oscillator 0.128 5 5 xtal oscillator 460 60 8 125 125 16 250 250 rc oscillator 8 50 50 pll 64/16 (1) 1.the pll generates a 64 mhz clock for the psc and a 16 mhz clock for the cpu. 700 700 clock prescaler n (2) 2.n is the frequency (in mhz) at the input of the clock prescaler n*30 n*50 256 4378c?avr?09/08 at90pwm1 24.2.2.1 example 1 calculate the expected current consumption in idle mode with a 8 mhz xtal oscillator feeding the pll to generate a 16 mhz clock further divided by 16 using the clkpr at v cc = 3.0v. the sys- tem clock is thus 1 mhz. peripherals and i/o are not active. reading from table 24-3 , we find that the xtal oscillator current is 0.125 ma, the pll current is 0.7 ma and the prescaler will need 16*30= 0.48 ma as it is clocked at 16 mhz. reading from figure 24-5 , we find that the idle current consumption of the core is ~0,17ma at v cc = 3.0v and f = 1mhz. the total current consumption in idle mode with the xtal and the pll gives: 24.2.2.2 example 2 calculate the expected current consumption in ac tive mode with a 4 mhz xtal oscillator clock further divided by 8 using the clkpr at v cc = 5.0v. the system clock is thus 0.5 mhz. periph- erals and i/o are not active. reading from table 24-3 , we find that the xtal oscillator current is 0.06 ma and the prescaler will need 4*50= 0.2 ma as it is clocked at 4mhz. reading from figure 24-1 , we find that the idle current consumption of the core is ~0,6 ma at v cc =5.0v and f = 0.5mhz. the total typical current consumption in active mode with the 4mhz xtal gives: i cc total 0.125 0.7 0.48 0.17 ++ + 1.475 ma ? ++ 0.86 ma ? 257 4378c?avr?09/08 at90pwm1 24.3 power-down supply current figure 24-9. power-down supply current vs. v cc (watchdog timer disabled) figure 24-10. power-down supply current vs. v cc (watchdog timer enabled) power-down supply current vs. v cc wa tchdog timer disa bled 105 c 85 c 25 c -40 c 0 1 2 3 4 5 6 7 22,533,544,555,5 v cc (v) i cc (ua) power-down supply current vs. v cc wa tchdog timer ena bled 105 c 85 c 25 c -40 c 0 2 4 6 8 10 12 14 22,533,544,555,5 v cc (v) i cc (ua) 258 4378c?avr?09/08 at90pwm1 24.4 pin pull-up figure 24-11. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 24-12. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) i/o pin (including pe1 & pe2) pull-up resistor current vs. input voltage vcc = 5.0 v 105 c 85 c 25 c -40 c -20 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) i/o pin (including pe1 & pe2) pull-up resistor current vs. input voltage vcc = 2.7 v 105 c 85 c 25 c -40 c -10 0 10 20 30 40 50 60 70 80 90 00,511,522,53 v op (v) i op (ua) 259 4378c?avr?09/08 at90pwm1 figure 24-13. reset pull-up resistor current vs. reset pin voltage (v cc = 5v) figure 24-14. reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) pe0 and reset pull-up resistor current vs. input voltage vcc = 5.0 v 105 c 85 c 25 c -40 c 0 20 40 60 80 100 120 0123456 v op (v) i op (ua) pe0 and reset pull-up resistor current vs. input voltage vcc = 2.7 v 105 c 85 c 25 c -40 c 0 10 20 30 40 50 60 70 00,511,522,53 v op (v) i op (ua) 260 4378c?avr?09/08 at90pwm1 24.5 pin driver strength figure 24-15. i/o pin source current vs. output voltage (v cc = 5v) figure 24-16. i/o pin source current vs. output voltage (v cc = 2.7v) i/o pin (including pe1 & pe2) source current vs. output voltage vcc = 5.0 v 105 c 85 c 25 c -40 c 0 5 10 15 20 25 4 4,2 4,4 4,6 4,8 5 5,2 v oh (v) i oh (ma) i/o pin (including pe1 & pe2) source current vs. output voltage vcc = 2.7 v 105 c 85 c 25 c -40 c 0 5 10 15 20 25 0 0,5 1 1,5 2 2,5 3 v oh (v) i oh (ma) 261 4378c?avr?09/08 at90pwm1 figure 24-17. i/o pin sink current vs. output voltage (v cc = 5v) figure 24-18. i/o pin sink current vs. output voltage (v cc = 2.7v) i/o pin (including pe1 & pe2) sink current vs. output voltage vcc = 5.0 v 105 c 85 c 25 c -40 c -5 0 5 10 15 20 25 0 0,2 0,4 0,6 0,8 1 v ol (v) i ol (ma) i/o pin (including pe1 & pe2) sink current vs. output voltage vcc = 2.7 v 105 c 85 c 25 c -40 c -5 0 5 10 15 20 25 0 0,5 1 1,5 2 2,5 3 v ol (v) i ol (ma) 262 4378c?avr?09/08 at90pwm1 24.6 pin thresholds and hysteresis figure 24-19. i/o pin input threshold voltage vs. v cc (vih, i/o pin read as '1') figure 24-20. i/o pin input threshold voltage vs. v cc (vil, i/o pin read as '0') i/o pin (including pe1 & pe2) input threshold voltage vs. v cc v ih, io pin rea d a s '1' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) i/o pin (including pe1 & pe2) input threshold voltage vs. v cc vil, io pin read as '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 263 4378c?avr?09/08 at90pwm1 figure 24-21. i/o pin input hysteresisvoltage vs. v cc figure 24-22. reset input threshold voltage vs. v cc (vih, reset pin read as '1') i/o pin input hysteresis vs. v cc 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis ( v) 85 c 25 c -40 c reset input threshold voltage vs. v cc v ih, reset pin rea d a s '1' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) 264 4378c?avr?09/08 at90pwm1 figure 24-23. reset input threshold voltage vs. v cc (vil, reset pin read as '0') figure 24-24. reset input pin hysteresis vs. v cc reset input threshold voltage vs. v cc v il, reset pin rea d a s '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 22,533,544,555,5 v cc (v) threshold (v) reset pin input hysteresis vs. v cc 105 c 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hysteresis (v) 265 4378c?avr?09/08 at90pwm1 figure 24-25. xtal1 input threshold voltage vs. v cc (xtal1 pin read as '1') figure 24-26. xtal1 input threshold voltage vs. v cc (xtal1 pin read as '0') xtal1 input threshold voltage vs. v cc xtal1 pin read as "1" 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) xtal1 input threshold voltage vs. v cc xtal1 pin read as "0" 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 22,533,544,555,5 v cc (v) threshold (v) 266 4378c?avr?09/08 at90pwm1 figure 24-27. pe0 input threshold voltage vs. v cc (pe0 pin read as '1') figure 24-28. pe0 input threshold voltage vs. v cc (pe0 pin read as '0') pe0 input threshold voltage vs. v cc v ih, pe0 pin rea d a s ' 1 ' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 4 22,533,544,555,5 v cc (v) threshold (v) pe0 input threshold voltage vs. v cc vil, pe0 pin read as '0' 105 c 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 267 4378c?avr?09/08 at90pwm1 24.7 bod thresholds and an alog comparator offset figure 24-29. bod thresholds vs. temperature (bodlevel is 4.3v) figure 24-30. bod thresholds vs. temperature (bodlevel is 2.7v) bod thresholds vs. temperature bodlv is 4.3 v rising vcc falling vcc 4,28 4,3 4,32 4,34 4,36 4,38 4,4 4,42 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) threshold (v) bod thresholds vs. temperature bodlv is 2.7 v rising vcc falling vcc 2,68 2,7 2,72 2,74 2,76 2,78 2,8 2,82 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) threshold (v) 268 4378c?avr?09/08 at90pwm1 figure 24-31. analog comparator offset voltage vs. common mode voltage (v cc =5v) note: corrected on at90pwm2b/3b to allow almost full scale use. figure 24-32. analog comparator offset voltage vs. common mode voltage (v cc =3v) note: corrected on at90pwm2b/3b to allow almost full scale use. analog comparator typical offset voltage vs. common mode voltage vcc = 5.0 v 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0123456 common mode voltage (v) analog comparator offset voltage (v) analog comparator typical offset voltage vs. common mode voltage vcc = 3.0 v 0 0,005 0,01 0,015 0,02 0,025 0,03 0,035 0,04 0,045 0 0,5 1 1,5 2 2,5 3 3,5 common mode voltage (v) analog comparator offset voltage (v) 269 4378c?avr?09/08 at90pwm1 24.8 analog reference figure 24-33. aref voltage vs. v cc figure 24-34. aref voltage vs. temperature aref voltage vs. v cc 105 c 85 c 25 c -40 c 2,3 2,35 2,4 2,45 2,5 2,55 2,6 22,533,544,555,5 vcc (v) aref (v) aref voltage vs. temperature 5.5 5 4.5 3 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 -60 -40 -20 0 20 40 60 80 100 120 temperature aref (v) 270 4378c?avr?09/08 at90pwm1 24.9 internal oscillator speed figure 24-35. watchdog oscillator frequency vs. v cc figure 24-36. calibrated 8 mhz rc oscillator frequency vs. temperature 105 c 85 c 25 c -40 c 96 98 100 102 104 106 108 110 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) f rc (khz) calibrated 8mhz rc oscillator frequency vs. temperature 10000 cycles sampled w ith 250ns 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 temperature osccal (mhz) 2.7 5 271 4378c?avr?09/08 at90pwm1 figure 24-37. calibrated 8 mhz rc oscillator frequency vs. v cc figure 24-38. calibrated 8 mhz rc oscillator frequency vs. osccal value int rc oscillator frequency vs. operating voltage 10000 cycles sampled w ith 250ns 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 22.533.544.555.5 v cc (v) f rc (mhz) 105 85 25 -40 0 2 4 6 8 10 12 14 16 18 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 oscca l f rc (mhz) 272 4378c?avr?09/08 at90pwm1 24.10 current consumption of peripheral units figure 24-39. brownout detector current vs. v cc figure 24-40. adc current vs. v cc (adc at 50 khz) brow nout detector current vs. v cc 105 c 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 45 22,533,544,555,5 v cc (v) i cc (ua) aref vs. v cc adc at 50 khz 85 c 25 c -40 c 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) t e m p l a t e to b e c h a r a c te r i z e d 273 4378c?avr?09/08 at90pwm1 figure 24-41. aref current vs. v cc (adc at 1 mhz) figure 24-42. analog comparator current vs. v cc aref vs. v cc adc at 1 mhz 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) analog comparator current vs. v cc 105 c 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 22,533,544,555,5 v cc (v) i cc (ua) 274 4378c?avr?09/08 at90pwm1 figure 24-43. programming current vs. v cc 24.11 current consumption in reset and reset pulse width figure 24-44. reset supply current vs. v cc (0.1 - 1.0 mhz, excluding current through the reset pull-up) programming current vs. v 85 ?c 25 ?c -40 ?c 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) cc reset supply current vs. v cc excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0,18 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) 275 4378c?avr?09/08 at90pwm1 figure 24-45. reset supply current vs. v cc (1 - 24 mhz, excluding current through the reset pull-up) figure 24-46. reset supply current vs. v cc (clock stopped, excluding current through the reset pull-up) reset supply current vs. v cc excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 3.0 v 2.7 v 0 0,5 1 1,5 2 2,5 3 3,5 4 0 5 10 15 20 25 frequency (mhz) i cc (ma) reset current vs. v cc (clock stopped) excluding current through the reset pullup 105 c 85 c 25 c -40 c -0,01 0 0,01 0,02 0,03 0,04 0,05 22,533,544,555,5 v cc (v) i cc (ma) 276 4378c?avr?09/08 at90pwm1 figure 24-47. reset pulse width vs. v cc reset pulse width vs. v cc ext clock 1 mhz 105 c 85 c 25 c -40 c 0 200 400 600 800 1000 1200 1400 1600 012 3456 v cc (v) pulsewidth (ns) 277 4378c?avr?09/08 at90pwm1 25. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) picr2h page 162 (0xfe) picr2l page 162 (0xfd) pfrc2b pcae2b pisel2b pelev2b pflte2b prfm2b3 prfm2b2 prfm2b1 prfm2b0 page 161 (0xfc) pfrc2a pcae2a pisel2a pelev2a pflte2a prfm2a3 prfm2a2 prfm2a1 prfm2a0 page 161 (0xfb) pctl2 ppre21 ppre20 pbfm2 paoc2b paoc2a parun2 pccyc2 prun2 page 160 (0xfa) pcnf2 pfifty2 palock2 plock2 pmode21 pmode20 pop2 pclksel2 pome2 page 157 (0xf9) ocr2rbh page 157 (0xf8) ocr2rbl page 157 (0xf7) ocr2sbh page 157 (0xf6) ocr2sbl page 157 (0xf5) ocr2rah page 156 (0xf4) ocr2ral page 156 (0xf3) ocr2sah page 156 (0xf2) ocr2sal page 156 (0xf1) pom2 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 page 163 (0xf0) psoc2 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a page 155 (0xef) picr1h (0xee) picr1l (0xed) pfrc1b pcae1b pisel1b pelev1b pflte1b prfm1b3 prfm1b2 prfm1b1 prfm1b0 page 161 (0xec) pfrc1a pcae1a pisel1a pelev1a pflte1a prfm1a3 prfm1a2 prfm1a1 prfm1a0 page 161 (0xeb) pctl1 prun1 page 160 (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) psoc1 ? ? psync11 psync10 ?poen1b ?poen1a (0xdf) picr0h page 162 (0xde) picr0l page 162 (0xdd) pfrc0b pcae0b pisel0b pelev0b pflte0b prfm0b3 prfm0b2 prfm0b1 prfm0b0 page 161 (0xdc) pfrc0a pcae0a pisel0a pelev0a pflte0a prfm0a3 prfm0a2 prfm0a1 prfm0a0 page 161 (0xdb) pctl0 ppre01 ppre00 pbfm0 paoc0b paoc0a parun0 pccyc0 prun0 page 158 (0xda) pcnf0 pfifty0 palock0 plock0 pmode01 pmode00 pop0 pclksel0 - page 157 (0xd9) ocr0rbh page 157 (0xd8) ocr0rbl page 157 (0xd7) ocr0sbh page 157 (0xd6) ocr0sbl page 157 (0xd5) ocr0rah page 156 (0xd4) ocr0ral page 156 (0xd3) ocr0sah page 156 (0xd2) ocr0sal page 156 (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) psoc0 ? ? psync01 psync00 ?poen0b ?poen0a page 155 (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) reserved ? ? ? ? ? ? ? ? (0xc5) reserved ? ? ? ? ? ? ? ? (0xc4) reserved ? ? ? ? ? ? ? ? (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) reserved ? ? ? ? ? ? ? ? (0xc1) reserved ? ? ? ? ? ? ? ? (0xc0) reserved ? ? ? ? ? ? ? ? (0xbf) reserved ? ? ? ? ? ? ? ? 278 4378c?avr?09/08 at90pwm1 (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) reserved ? ? ? ? ? ? ? ? (0xbc) reserved ? ? ? ? ? ? ? ? (0xbb) reserved ? ? ? ? ? ? ? ? (0xba) reserved ? ? ? ? ? ? ? ? (0xb9) reserved ? ? ? ? ? ? ? ? (0xb8) reserved ? ? ? ? ? ? ? ? (0xb7) reserved ? ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) ac2con ac2en ac2ie ac2is1 ac2is0 ac2sade- ac2m2 ac2m1 ac2m0 page 178 (0xad) ac0con ac0en ac0ie ac0is1 ac0is0 - ac0m2 ac0m1 ac0m0 page 177 (0xac) reserved ? ? ? ? ? ? ? ? page 258 (0xab) reserved ? ? ? ? ? ? ? ? page 258 (0xaa) reserved ? ? ? ? ? ? ? ? page 257 (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) pim2 - - pseie2 peve2b peve2a - - peope2 page 164 (0xa4) pifr2 - - psei2 pev2b pev2a prn21 prn20 peop2 page 164 (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) pim0 - - pseie0 peve0b peve0a - - peope0 page 164 (0xa0) pifr0 - - psei0 pev0b pev0a prn01 prn00 peop0 page 164 (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr1b8 page 120 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1b3 ocr1b2 ocr1b1 ocr1b0 page 120 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr1a8 page 120 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1a3 ocr1a2 ocr1a1 ocr1a0 page 120 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 page 121 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 page 121 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 page 120 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 page 120 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ? page 119 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 118 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 page 116 (0x7f) didr1 ? ? acmp0d amp0pd amp0nd adc10d/acmp1d adc9d/amp1pd adc8d/amp1nd page 199 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d/acmpmd adc2d/acmp2d adc1d adc0d page 199 (0x7d) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 279 4378c?avr?09/08 at90pwm1 (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 page 194 (0x7b) adcsrb adhsm ? ? adascr adts3 adts2 adts1 adts0 page 196 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 195 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 page 198 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / page 198 (0x77) (0x76) amp0csr amp0en - amp0g1 amp0g0 - amp0ts2 amp0ts1 amp0ts0 page 202 (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 page 121 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 page 94 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) reserved ? ? ? ? ? ? ? ? (0x6b) reserved ? ? ? ? ? ? ? ? (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 74 (0x68) reserved ? ? ? ? ? ? ? ? (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 page 31 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prpsc2 prpsc1 prpsc0 prtim1 prtim0 prspi ? pradc page 39 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 35 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 page 50 0x3f (0x5f) sreg ithsvnz c page 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 13 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen page 211 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr spips ? ?pud ? ? ivsel ivce page 56 & page 65 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 46 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se page 37 0x32 (0x52) msmcr monitor stop mode control register reserved 0x31 (0x51) mondr monitor data register reserved 0x30 (0x50) acsr acckdiv ac2if ?ac0if ?ac2o ?ac0o page 179 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 page 174 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x page 173 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 172 0x2b (0x4b) reserved ? ? ? ? ? ? ? ? 0x2a (0x4a) reserved ? ? ? ? ? ? ? ? 0x29 (0x49) pllcsr - - - - - pllf plle plock page 33 0x28 (0x48) ocr0b ocr0b7 ocr0b6 ocr0b5 ocr0b4 ocr0b3 ocr0b2 ocr0b1 ocr0b0 page 94 0x27 (0x47) ocr0a ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 page 93 0x26 (0x46) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 page 93 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 page 92 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 page 89 0x23 (0x43) gtccr tsm icpsel1 ? ? ? ? ?psrsync page 77 0x22 (0x42) eearh ? ? ? ? eear11 eear10 eear9 eear8 page 19 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 19 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 page 20 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere page 20 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 page 25 0x1d (0x3d) eimsk ? ? ? ? int3 int2 int1 int0 page 75 0x1c (0x3c) eifr ? ? ? ? intf3 intf2 intf1 intf0 page 75 0x1b (0x3b) gpior3 gpior37 gpior36 gpior35 gpior34 gpior33 gpior32 gpior31 gpior30 page 25 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 280 4378c?avr?09/08 at90pwm1 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the at90pwm1 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1a (0x3a) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 page 25 0x19 (0x39) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gpior10 page 25 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) reserved ? ? ? ? ? ? ? ? 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 page 122 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 page 94 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) porte ? ? ? ? ? porte2 porte1 porte0 page 73 0x0d (0x2d) ddre ? ? ? ? ? dde2 dde1 dde0 page 73 0x0c (0x2c) pine ? ? ? ? ? pine2 pine1 pine0 page 73 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 73 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 73 0x09 (0x29) pind pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 page 73 0x08 (0x28) ? ? ? ? ? ? ? ? ? ? 0x07 (0x27) ? ? ? ? ? ? ? ? ? ? 0x06 (0x26) ? ? ? ? ? ? ? ? ? ? 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 72 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 72 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 73 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x00 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 281 4378c?avr?09/08 at90pwm1 26. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? cz, n,v,c,h1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 282 4378c?avr?09/08 at90pwm1 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 none 2 cbi p,b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions mnemonics operands description operation flags #clocks 283 4378c?avr?09/08 at90pwm1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 284 4378c?avr?09/08 at90pwm1 27. ordering information note: all packages are pb free, fully lhf note: this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa tion and minimum quantities. speed (mhz) power supply ordering code package operation range 16 2.7 - 5.5v at90pwm1-16su so24 extended (-4 0 c to 105 c) 16 2.7 - 5.5v at90pwm1-16mu qfn32 extended (-4 0 c to 105 c) 285 4378c?avr?09/08 at90pwm1 28. package information package type so24 24-lead, 0.300? body width, plastic gullwing small outline package (soic) qfn32 32-lead, quad flat no lead 286 4378c?avr?09/08 at90pwm1 28.1 so24 287 4378c?avr?09/08 at90pwm1 28.2 qfn32 4378c?avr?09/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, expres s or implied, by estoppel or otherwise, to any intellectual property right is granted by this documen t or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. 289 4378c?avr?09/08 at90pwm1 29. errata ? psc : double end-of-cycle interrupt request in centered mode ? adc : conversion accuracy ? 1. psc : double end-of-cycle interrupt request in centered mode in centered mode, after the ?expected? end-of-cycle interrupt, a second unexpected inter- rupt occurs 1 psc cycle after the previous interrupt. work around: while cpu cycle is lower than psc clock, the cpu sees only one interrupt request. for psc clock period greater than cpu cycle, the seco nd interrupt request must be cleared by software. 2. adc : conversion accuracy the conversion accuracy degrades when the adc clock is 2 mhz. work around: when a 10 bit conversion accuracy is required, use an adc clock of 1 mhz or below. at 2 mhz the adc can be used as a 7 bits adc. 290 4378c?avr?09/08 at90pwm1 30. datasheet revision history for at90pwm1 please note that the referring page numbers in this section are referred to this document. the referring revision in this section are referring to the document revision. 30.1 changes from 4378a to 4378b 1. psc : the balance flank width modulation is done on-time 1 rather than on-time 0 (correction of figures) 2. updated ?device clocking options select at90pwm1? on page 28 3. updated ?start-up times when the pll is selected as system clock? on page 32 4. updated ?calibrated internal rc oscillator? on page 30 5. updated ?adc noise canceler? on page 188 6. updated ?adc auto trigger source selection for non amplified conversions? on page 197 7. updated ?adc auto trigger source selection for amplified conversions? on page 197 8. updated ?amplifier? on page 199 9. updated ?amplifier 0 control and status register ? amp0csr? on page 202 10. updated ?amp0 auto trigger source selection? on page 203 11. updated temperature range in ?dc characteristics? on page 239 12. updated vhysr in ?dc characteristics? on page 239 13. added ?calibrated internal rc oscillator accuracy? on page 241 14. updated ?maximum speed vs. vcc? on page 242 15. updated ?adc characteristics? on page 245 16. updated ?example 1? on page 254 17. updated ?example 2? on page 254 18. updated ?example 3? on page 255 19. added ?i/o pin input hysteresisvoltage vs. vcc? on page 263 20. specify the ?aref voltage vs. temperature? on page 269 21. updated figure 24-36 on page 270 22. updated figure 24-37 on page 271 23. updated figure 24-38 on page 271 24. updated ?ordering information? on page 284 25. updated ?package information? on page 285 30.2 changes from 4378b to 4378c 1. minor corrections throughout the document. 291 4378c?avr?09/08 at90pwm1 table of contents 1 history ....................................................................................................... 2 2 disclaimer ................................................................................................. 2 3 pin configurations ................................................................................... 2 3.1 pin descriptions .......................................................................................................4 4 overview ................................................................................................... 5 4.1 block diagram .........................................................................................................6 4.2 pin descriptions .......................................................................................................7 4.3 about code examples .............................................................................................8 5 avr cpu core .......................................................................................... 9 5.1 introduction .............................................................................................................. 9 5.2 architectural overview .............................................................................................9 5.3 alu ? arithmetic logic unit ...................................................................................10 5.4 status register ......................................................................................................11 5.5 general purpose register file ..............................................................................12 5.6 stack pointer .........................................................................................................13 5.7 instruction execution timing .................................................................................13 5.8 reset and interrupt handling .................................................................................14 6 memories ................................................................................................ 17 6.1 in-system reprogrammable flash program memory ...........................................17 6.2 sram data memory ..............................................................................................17 6.3 eeprom data memory ........................................................................................19 6.4 i/o memory ............................................................................................................25 6.5 general purpose i/o registers .............................................................................25 7 system clock ......................................................................................... 27 7.1 clock systems and their distribution .....................................................................27 7.2 clock sources .......................................................................................................28 7.3 default clock source .............................................................................................29 7.4 low power crystal oscillator .................................................................................29 7.5 calibrated internal rc oscillator ...........................................................................30 7.6 pll ....................................................................................................................... .32 7.7 128 khz internal oscillator ....................................................................................34 7.8 external clock .......................................................................................................34 292 4378c?avr?09/08 at90pwm1 7.9 clock output buffer ...............................................................................................35 7.10 system clock prescaler ......................................................................................35 8 power management and sleep modes ................................................. 37 8.1 idle mode ...............................................................................................................38 8.2 adc noise reduction mode ..................................................................................38 8.3 power-down mode .................................................................................................38 8.4 standby mode .......................................................................................................38 8.5 power reduction register .....................................................................................39 8.6 minimizing power consumption ............................................................................40 9 system control and reset .................................................................... 42 9.1 internal voltage reference ....................................................................................47 9.2 watchdog timer ....................................................................................................48 10 interrupts ................................................................................................ 53 10.1 interrupt vectors in at90pwm1 ..........................................................................53 11 i/o-ports .................................................................................................. 58 11.1 introduction ..........................................................................................................58 11.2 ports as general digital i/o .................................................................................59 11.3 alternate port functions ......................................................................................63 11.4 register description for i/o-ports ........................................................................72 12 external interrupts ................................................................................. 74 13 timer/counter0 and timer/counter1 prescalers ................................ 76 14 8-bit timer/counter0 with pwm ............................................................ 79 14.1 overview ..............................................................................................................79 14.2 timer/counter clock sources ..............................................................................80 14.3 counter unit ........................................................................................................80 14.4 output compare unit ...........................................................................................81 14.5 compare match output unit ................................................................................83 14.6 modes of operation .............................................................................................84 14.7 timer/counter timing diagrams ..........................................................................88 14.8 8-bit timer/counter register description ............................................................89 15 16-bit timer/counter1 with pwm .......................................................... 96 15.1 overview ..............................................................................................................96 15.2 accessing 16-bit registers ..................................................................................98 293 4378c?avr?09/08 at90pwm1 15.3 timer/counter clock sources ............................................................................101 15.4 counter unit ......................................................................................................102 15.5 input capture unit .............................................................................................103 15.6 output compare units .......................................................................................104 15.7 compare match output unit ..............................................................................106 15.8 modes of operation ...........................................................................................107 15.9 timer/counter timing diagrams ........................................................................115 15.10 16-bit timer/counter register description ......................................................116 16 power stage controller ? (psc0, psc2) ............................................ 123 16.1 features ............................................................................................................123 16.2 overview ............................................................................................................123 16.3 psc description ................................................................................................124 16.4 signal description ..............................................................................................126 16.5 functional description .......................................................................................128 16.6 update of values ...............................................................................................133 16.7 enhanced resolution ........................................................................................133 16.8 psc inputs ........................................................................................................137 16.9 psc input mode 1: stop signal, jump to opposite dead-time and wait .........142 16.10 psc input mode 2: stop signal, execute opposite dead-time and wait .......143 16.11 psc input mode 3: stop signal, execute opposite while fault active .............144 16.12 psc input mode 4: deactivate outputs without changing timing. ....................144 16.13 psc input mode 5: stop signal and insert dead-time ....................................145 16.14 psc input mode 6: stop signal, jump to opposite dead-time and wait. ......146 16.15 psc input mode 7: halt psc and wait for software action ............................146 16.16 psc input mode 8: edge retrigger psc .........................................................147 16.17 psc input mode 9: fixed frequency edge retrigger psc .............................148 16.18 psc input mode 14: fixed frequency edge retrigger psc and disactivate output 149 16.19 psc2 outputs ..................................................................................................151 16.20 analog synchronization ...................................................................................152 16.21 interrupt handling ............................................................................................152 16.22 psc synchronization .......................................................................................152 16.23 psc clock sources .........................................................................................153 16.24 interrupts .........................................................................................................154 16.25 psc register definition ...................................................................................154 16.26 psc2 specific register ...................................................................................163 294 4378c?avr?09/08 at90pwm1 17 serial peripheral interface ? spi ......................................................... 166 17.1 features ............................................................................................................166 17.2 ss pin functionality ..........................................................................................171 17.3 data modes .......................................................................................................174 18 analog comparator ............................................................................. 176 18.1 overview ............................................................................................................176 18.2 analog comparator register description ..........................................................177 19 analog to digital converter - adc ..................................................... 181 19.1 features ............................................................................................................181 19.2 operation ...........................................................................................................183 19.3 starting a conversion ........................................................................................183 19.4 prescaling and conversion timing ....................................................................184 19.5 changing channel or reference selection .......................................................186 19.6 adc noise canceler .........................................................................................188 19.7 adc conversion result .....................................................................................192 19.8 adc register description ..................................................................................194 19.9 amplifier .............................................................................................................199 19.10 amplifier control registers ..............................................................................202 20 debugwire on-chip debug system .................................................. 204 20.1 features ............................................................................................................204 20.2 overview ............................................................................................................204 20.3 physical interface ..............................................................................................204 20.4 software break points .......................................................................................205 20.5 limitations of debugwire .................................................................................205 20.6 debugwire related register in i/o memory ....................................................205 21 boot loader support ? read-while -write self-programming ......... 205 21.1 boot loader features ........................................................................................206 21.2 application and boot loader flash sections .....................................................206 21.3 read-while-write and no read-while-write flash sections ............................206 21.4 boot loader lock bits .......................................................................................209 21.5 entering the boot loader program ....................................................................210 21.6 addressing the flash during self-programming ...............................................212 21.7 self-programming the flash ..............................................................................213 22 memory programming ......................................................................... 219 295 4378c?avr?09/08 at90pwm1 22.1 program and data memory lock bits ...............................................................219 22.2 fuse bits ............................................................................................................221 22.3 psc output behaviour during reset ................................................................221 22.4 signature bytes .................................................................................................223 22.5 calibration byte .................................................................................................223 22.6 parallel programming parameters, pin mapping, and commands ...................223 22.7 serial programming pin mapping ......................................................................225 22.8 parallel programming ........................................................................................225 22.9 serial downloading ............................................................................................234 23 electrical characteristics (1) ................................................................................................ 238 23.1 absolute maximum ratings* .............................................................................238 23.2 dc characteristics .............................................................................................239 23.3 external clock drive characteristics .................................................................241 23.4 maximum speed vs. v cc .......................................................................................................................... 24 2 23.5 pll characteristics ...........................................................................................242 23.6 spi timing characteristics ................................................................................243 23.7 adc characteristics ..........................................................................................245 23.8 parallel programming characteristics ...............................................................247 24 at90pwm1 typical characteristics ................................................... 249 24.1 active supply current ........................................................................................250 24.2 idle supply current ............................................................................................252 24.3 power-down supply current .............................................................................257 24.4 pin pull-up .........................................................................................................258 24.5 pin driver strength ............................................................................................260 24.6 pin thresholds and hysteresis ..........................................................................262 24.7 bod thresholds and analog comparator offset ..............................................267 24.8 analog reference ..............................................................................................269 24.9 internal oscillator speed ...................................................................................270 24.10 current consumption of peripheral units ........................................................272 24.11 current consumption in reset and reset pulse width ....................................274 25 register summary ............................................................................... 277 26 instruction set summary .................................................................... 281 27 ordering information ........................................................................... 284 28 package information ............................................................................ 285 296 4378c?avr?09/08 at90pwm1 28.1 so24 .................................................................................................................286 28.2 qfn32 ...............................................................................................................287 29 errata ..................................................................................................... 289 30 datasheet revision history for at90pwm1 ...................................... 290 30.1 changes from 4378a to 4378b .........................................................................290 30.2 changes from 4378b to 4378c .........................................................................290 4378c?avr?09/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, expres s or implied, by estoppel or otherwise, to any intellectual property right is granted by this documen t or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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